Hi Laurent,
On 26/06/17 19:12, Laurent Pinchart wrote:
> The H3 ES1.x exhibits dot clock duty cycle stability issues. We can work
> around them by configuring the DPLL to twice the desired frequency,
> coupled with a /2 post-divider. This isn't needed on other SoCs and
> breaks HDMI output on M3-W
From: Jernej Skrabec
Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.
Add a pre_init function for this kind of work.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
inclu
On Tuesday, August 1, 2017 9:58:17 AM PDT Ben Widawsky wrote:
> v2:
> - Support sprite plane.
> - Support pipe C/D limitation on GEN9.
>
> v3:
> - Rename structure (Ville)
> - Handle GLK (Ville)
>
> v4:
> - Fix PIPE_C check, introduced in v2 (Daniel)
> - Whitespace fix (Daniel)
>
> C
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and will be enabled later.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 170
From: Jernej Skrabec
Some custom phys don't support hpd interrupts. Add support for polling
such events.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.
From: Icenowy Zheng
Allwinner H3 has two special TCONs without channel 0.
Add support for this kind of TCON.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++---
drivers/gpu/drm/sun4i/sun4i_
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
-
Hi Laurent,
On 26/06/17 19:12, Laurent Pinchart wrote:
> The VSP supports both header and headerless display lists. The latter is
> easier to use when the VSP feeds data directly to the DU in continuous
> mode, and the driver thus uses headerless display lists for DU operation
> and header display
Hello Srinivas,
On 08/01/2017 02:52 PM, Srinivas Kandagatla wrote:
As example, if you configure bus in Left justified format with 24 bits
sample length, 32 bits application samples should be truncated to 24
bits samples at ADV7533 I2S interface level (LSB dropped).
>>
>>> May be we
The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.
Add the related device nodes.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
Hi Laurent,
Thankyou for the patch,
On 26/06/17 19:12, Laurent Pinchart wrote:
> On Gen3 SoCs DPAD0 routing is configured through the last CRTC group,
> unlike on Gen2 where it is configured through the first CRTC group. Fix
> the driver accordingly.
>
> Fixes: 2427b3037710 ("drm: rcar-du: Add R
Allwinner H3 features a "Display Engine 2.0", which needs some support
to be present in the DRM driver.
This patchset is now a basical version, which dropped some features I
used to submitted:
- TVE support (not so high priority now)
- Multi-pipeline support (also not so high priority now due to n
Hello Srinivas,
On 08/01/2017 12:49 AM, srinivas.kandaga...@linaro.org wrote:
> From: Srinivas Kandagatla
>
> ADV7533 only supports audio samples word width from 16-24 bits.
> This patch restricts the audio sample sizes to the supported ones,
> so that sound card does not report wrong list of su
Hi Laurent,
Last one - (and I thought I'd already done this one in the last batch .. but
perhaps I lost it before hitting send)
On 26/06/17 19:12, Laurent Pinchart wrote:
> The R-Car H3 ES2.0 VSP-DL instance has two LIF entities and can drive
> two display pipelines at the same time. Refactor the
The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.
So export it to the device tree binding header.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +--
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files cha
Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.
Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.
So allow CLK_DE to set CLK_P
From: Jernej Skrabec
Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.
For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gp
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++
1 file changed, 21 insertions(+), 4 deletio
From: Jernej Skrabec
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI. There's also some graphics post-process
function that is missing on mixer1, however, as we currently support
none of these functions, the only difference that is shown to
Hi Laurent,
On 26/06/17 19:12, Laurent Pinchart wrote:
> On R-Car H3 ES2.0, DU channels 0 and 3 are served by two separate
> pipelines from the same VSP. Support this in the DU driver.
>
> Signed-off-by: Laurent Pinchart
This looks good to me.
Minor nit / comment can be safely ignored. Mostly
On Tuesday, August 1, 2017 3:47:53 PM PDT Ben Widawsky wrote:
> On 17-08-01 15:43:50, Kenneth Graunke wrote:
> >On Tuesday, August 1, 2017 9:58:17 AM PDT Ben Widawsky wrote:
> >> v2:
> >> - Support sprite plane.
> >> - Support pipe C/D limitation on GEN9.
> >>
> >> v3:
> >> - Rename structure
Hi Laurent,
Thanks for the fast update.
On 01/08/17 18:20, Laurent Pinchart wrote:
> On Gen3 SoCs DPAD0 routing is configured through the last CRTC group,
> unlike on Gen2 where it is configured through the first CRTC group. Fix
> the driver accordingly.
>
> Fixes: 2427b3037710 ("drm: rcar-du: A
Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.
Enable the HDMI output in Orange Pi PC device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/a
On 18/07/2017 10:43 AM, Takashi Iwai wrote:
Hi,
this is a summer cleanup sale, a patchset containing various fixes for
mgag200 driver taken from openSUSE / SUSE kernels. They have been in
our kernels for ages, so at least they are supposed to be stable.
Most of patches came from Egbert, and on
https://bugs.freedesktop.org/show_bug.cgi?id=101988
--- Comment #10 from Michel Dänzer ---
(In reply to newincpp from comment #5)
> [ 107.804672] amdgpu :01:00.0: SI support provided by radeon.
> [ 107.804674] amdgpu :01:00.0: Use radeon.si_support=0
> amdgpu.si_support=1 to override.
https://bugs.freedesktop.org/show_bug.cgi?id=102008
--- Comment #1 from Michel Dänzer ---
Please track down which commit exactly broke it.
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https://bugs.freedesktop.org/show_bug.cgi?id=102004
--- Comment #3 from Michel Dänzer ---
Could be bug 101969.
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On 19 July 2017 at 00:47, Takashi Iwai wrote:
> Hi,
>
> here is another clearance sale, a patchset containing fixes for ast
> driver, dug from openSUSE / SUSE kernels. All fixes came from
> Egbert.
I've merged this set as is.
Thanks,
Dave.
>
>
> thanks,
>
> Takashi
>
> ===
>
> Egbert Eich (5):
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/nouveau/nv50_display.c
between commit:
4a5431af19bc ("drm/nouveau/kms/nv50: update vblank state in response to
modeset actions")
from Linus' tree and commit:
3c847d6cdadb ("drm/nouveau: Convert nou
Ping? Just wanted to make sure this didn't get missed.
Thanks,
Alex
On Thu, Jul 27, 2017 at 12:00 PM, Alex Deucher wrote:
> Hi Dave,
>
> New features for 4.14:
> - Stop reprogramming the MC, the vbios already does this in asic_init
> - Reduce internal gart to 256M (this does not affect the tt
On Tue, 2017-08-01 at 17:30 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
>
> Thank you for the patch.
>
> On Tuesday 01 Aug 2017 10:31:34 Hean Loong, Ong wrote:
> >
> > From: Ong Hean Loong
> >
> > Driver for Intel FPGA Video and Image Processing
> > Suite Frame Buffer II. The driver only s
On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng wrote:
> Allwinner H3 features a "Display Engine 2.0", which needs some support
> to be present in the DRM driver.
>
> This patchset is now a basical version, which dropped some features I
> used to submitted:
> - TVE support (not so high priority now)
https://bugs.freedesktop.org/show_bug.cgi?id=101946
--- Comment #28 from Robin ---
(In reply to Luke A. Guest from comment #27)
> > FWIW I don't think any of these patches are relevant to you then.
>
> Not strictly true. As I said, Alex pointed me at this page to try his
> patches. I believe all
On 08/02/2017 12:32 AM, Laurent Pinchart wrote:
>> +
>> +cec_register_cec_notifier(cec->adap, cec->notify);
>> +
>> +return 0;
>> +}
>> +
>> +static int dw_hdmi_cec_remove(struct platform_device *pdev)
>> +{
>> +struct dw_hdmi_cec *cec = platform_get_drvdata(pdev);
>> +
>> +cec_unre
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