On 06/02/2017 11:48 PM, Eric Anholt wrote:
Hans Verkuil writes:
The bo->resv pointer could be NULL, leading to kernel oopses like the one below.
It looks like .fb_probe -> drm_fbdev_cma_create() -> drm_gem_cma_create() would
end up not initializing resv, because we're doing that in vc4_bo_crea
https://bugzilla.kernel.org/show_bug.cgi?id=194761
--- Comment #36 from Jean Delvare (jdelv...@suse.de) ---
The patch in comment #33 is what I came up with (see comment #26) and it works
OK for me. Note that the second part of the patch isn't needed though, the
added condition will always be tree
https://bugzilla.kernel.org/show_bug.cgi?id=194761
--- Comment #37 from Jean Delvare (jdelv...@suse.de) ---
Alex, is the fix in comment #35 possibly related to this bug, or you just
happened to find it while reading the code?
--
You are receiving this mail because:
You are watching the assignee
https://bugzilla.kernel.org/show_bug.cgi?id=194761
--- Comment #38 from Marek Olšák (mar...@gmail.com) ---
The second possible fix is a bug fix by itself (not just for this issue), seems
like an important fix affecting Mesa, and may change the outcome of the first
fix. (which we are still uncertai
2017-05-15 8:20 GMT+03:00 Tommi Rantala :
> 2017-05-15 3:03 GMT+03:00 Ben Skeggs :
>> On 05/15/2017 01:10 AM, Tommi Rantala wrote:
>>>
>>> Hi,
>>
>> Hey Tommi,
>>
>> Thanks for bisecting this. It's rather unexpected that you should be seeing
>> problems here, but, the commit makes sense for it at
On Thu, Jun 01, 2017 at 10:31:10AM +0200, Hans Verkuil wrote:
> This will change. Patches to fix the config handling are pending for 4.12.
>
> Here you can see the pending patches:
> https://git.linuxtv.org/hverkuil/media_tree.git/log/?h=drm-cec
>
> The patches from 'cec-notifier.h: handle unreac
On Fri, Jun 02, 2017 at 11:06:24AM +0200, Hans Verkuil wrote:
> On 06/02/17 08:43, Jose Abreu wrote:
> > Hi Hans,
> >
> >
> > On 02-06-2017 07:31, Hans Verkuil wrote:
> >> On 06/01/2017 03:47 PM, Neil Armstrong wrote:
> >>> On 05/30/2017 04:23 PM, Russell King wrote:
> Add a CEC driver for t
The encoder drivers use drm_of_find_possible_crtcs to get upstream
crtcs from the device tree using of_graph. For the results to be
correct, encoders must be probed/bound after _all_ crtcs have been
created. The existing code uses a depth first recursive traversal
of the of_graph, which means the e
We are working with new desktop that have the NVIDIA NV118
chipset.
During boot, the display becomes unusable at the point where the
nouveau driver loads. We have reproduced on 4.8, 4.11 and linux
master (4.12-rc3).
Dmesg log is attached.
Is this a known issue? Anything we can do to help?
Thank
On Fri, Jun 02, 2017 at 06:02:28AM +0100, Jose Abreu wrote:
> You should check that CEC is: not in standy, acknowledges
> broadcast messages, signal free time is 5bit period, and not lost
> arbitration, which basically means CEC_CTRL must be 0x2 and
> IH_CEC_STAT0 must not have ARB_LOST set.
If AR
The Sinlinx SinA31s has an HDMI connector wired to the HDMI pins
from the SoC.
Enable the display pipeline and the HDMI output.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/d
Now that we support the HDMI controller on the A31 SoC, we can add it
to the device tree.
This adds a device node for the HDMI controller, and the of_graph nodes
connecting it to the 2 TCONs.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31.dtsi | 55 +
The MSI Primo81 tablet has a micro HDMI connector at the bottom.
This is connected to the SoCs HDMI output.
Enable the display pipeline and the HDMI output.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 25 +
1 file changed, 25 insertions(+)
The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.
Export them so they can be referenced in the device tree.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.h | 8 ++--
include/dt-bindings/clock/sun6i-a31-ccu.h | 4
2 files
On 05/25/2017 01:23 PM, Archit Taneja wrote:
> Hi Philippe,
>
> Thanks a lot for creating a bridge driver for this.
>
> Copying some Hisilicon and Rockchip folks so that they can consider adapting
> to this.
>
> Some comments below.
Hi Archit,
and many thanks for your great comments.
>
> On
On Fri, Jun 2, 2017 at 10:56 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:
>
> Somehow the CC's got removed in my previous reply, adding them back. See
> one additional comment below.
>
>
> > On Fri, 2017-05-26 at
Hi,
Changes since v1:
- proper locking within omap_connector_hpd_cb()
- include the correct linux/mutex.h in omap_connector and tpd driver.
this series will add support for HPD in omapdrm. Instead of polling for HPD
changes we can use interrupts to be notified of HPD change, thus we can react to
This patch set contain 3 patches. Another 6 patches in previous version
was already merged in v7 and v9.
- First patch sets the PWM freqency to match data in panel vbt.
- Next patch adds heuristic to determine whether we should use AUX
or PWM pin to adjust panel backlight brightness.
- Last patch
Hi everyone,
This series adds support for the HDMI controller found on Allwinner
A31/A31s SoCs. It builds upon Maxime's work that added support for
the HDMI controller on the Allwinner A10s SoC.
The HDMI controllers in the older generation Allwinner SoCs is very
similar. The A10/A10s/A20 all have
The HDMI driver enables the bus and mod clocks in the bind function, but
does not disable them if it then bails our due to any errors. Neither
does it disable the clocks in the unbind function.
Fix this by adding a proper error path to the bind function, and
clk_disable_unprepare calls to the unbi
On Fri, Jun 2, 2017 at 11:25 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > This patch adds option to enable dynamic backlight for eDP
> > panel that supports this feature via DPCD register and
> > set minimum
On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different
Signed-off-by: Geert Uytterhoeven
Acked-by: Chanho Min
---
v3:
- Add Acked-by,
v2:
- New.
---
arch/arm64/boot/dts/lg/lg1313.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi
b/arch/arm64/boot/dts/lg/lg1313.dtsi
index e703e1149c75708
The DDC block for the HDMI controller is different on the A31.
This patch adds the register definitions.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
b/drive
The HPD signal can be used for detecting HDMI cable plug and unplug event
without the need for polling the status of the line.
This will speed up detecting such event because we do not need to wait for
the next poll event to notice the state change.
Signed-off-by: Peter Ujfalusi
---
drivers/gpu/
Signed-off-by: Geert Uytterhoeven
Acked-by: Rob Herring
Acked-by: Chanho Min
---
v3:
- Add Acked-by,
v2:
- Add Acked-by,
- Rebased.
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi
b/arch/arm64/
Hi all,
This patch series fixes misspellings of various standard DT properties
in DT binding documentation, DTS files, and examples.
While most of these are harmless, some of them may cause hard-to-debug
failures.
Changes compared to v3:
- Drop patches that have been applied already,
On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.
Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its p
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency divisor is still
within 25% of the desired value.
Change-Id: I96221608e1288f
Signed-off-by: Geert Uytterhoeven
Acked-by: Rob Herring
---
v3:
- No changes,
v2:
- Add Acked-by.
---
Documentation/devicetree/booting-without-of.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/booting-without-of.txt
b/Documentation/devicetr
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> Add heuristic to decide that AUX or PWM pin should use for
> backlight brightness adjustment and modify i915 param description
> to have auto, force disable, and force enable.
>
> The heuristic to determine that using AUX pin is be
Fixes: 8cceda5349377e30 ("dt-bindings: Add bindings for the Amlogic Meson
dw-hdmi extension")
Signed-off-by: Geert Uytterhoeven
---
v3:
- New.
---
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentat
The DDC parent clock on the A31 SoC is also conveniently named
"hdmi-ddc", which results in a name collision when the hdmi driver
registers its internal DDC divider clock.
Rename the internal clock to "hdmi-ddc-divider".
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
The HDMI controller found in the A31 SoCs is slightly different
from the one already supported, which is found in the A10s:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Sep
On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different
If we want to have vblank on both pipelines at the same time, we need
to call drm_vblank_init with num_crtcs = 2.
Instead, since the crtc init calls correctly set mode_config.num_crtc,
we can move the drm_vblank_init call to after the crtc init code is
called, which is the component bind part. The
On systems with 2 TCONs such as the A31, it is possible to demux the
output of the TCONs to one encoder.
Add support for this for the A31.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 ++
1 file changed, 61 insertions(+)
diff --git
Version 3:
- stm/ltdc: Use panel-bridge (-170 lines), thanks to comments of Eric Anholt,
Boris Brezillon, Archit Taneja & Andrzej Hajda.
- Synopsys dsi: Add dw_mipi_dsi.h (forgotten in v2), thanks to comments of
Neil Armstrong.
- Synopsys dsi/dw-mipi-dsi.c: add dw_mipi_dsi_dphy_init() &
dw_mi
There is no need anymore to have a "st-display-subsystem" parent node
in the device tree for the ltdc.
Signed-off-by: Philippe CORNU
---
Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/st,stm
The A31 Humminbird has an HDMI connector wired to the HDMI pins
on the SoC. Enable HDMI support for this board.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-hummi
The HDMI controller found in earlier Allwinner SoCs have slight
differences:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit
Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/bridge/synopsys/Kconfig |9 +
drivers/gpu/drm/bridge/synopsys/Makefile |2 +
drivers/g
The A31's HDMI controller's TMDS clock is slightly different.
There is an offset of 1 between the divider value and the actual
value programmed into the registers.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 1 +
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 7 +
On the A31, the HDMI TMDS clock has a different value offset for the
divider.
This patch adds support for custom offsets to the TMDS clock.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(
On 02.06.2017 17:12, Alex Deucher wrote:
> On Fri, Jun 2, 2017 at 3:35 AM, Florian Echtler wrote:
>>
>> [ 166.853787] [drm:radeon_dp_link_train_cr] clock recovery at voltage 0
>> pre-emphasis 0
>> [ 166.853788] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>> [ 166.855953] [drm
On Fri, Jun 02, 2017 at 11:32:21AM +0200, Christian König wrote:
> Hi Bjorn,
>
> sorry for not responding earlier and thanks for picking this thread
> up again.
>
> Am 01.06.2017 um 22:14 schrieb Bjorn Helgaas:
> >[+cc ADMGPU, DRM folks]
> >
> >On Tue, May 09, 2017 at 06:49:07PM +0200, Christian
On Fri, Jun 02, 2017 at 11:28:08AM +0200, Hans Verkuil wrote:
> The 'signal_free_time' argument of adap_transmit will have the recommended
> signal free time. You can test against the CEC_SIGNAL_FREE_TIME_* defines
> from media/cec.h. You probably saw this already, but just in case you missed
> thi
If the hpd_gpio is valid, use interrupt handler to react to HPD changes.
In case the hpd_gpio is not valid, try to enable hpd detection on the
encoder if it supports it.
Signed-off-by: Peter Ujfalusi
---
drivers/gpu/drm/omapdrm/displays/connector-hdmi.c | 104 ++
1 file chang
Use interrupt handler for hpd GPIO to react to HPD changes.
Signed-off-by: Peter Ujfalusi
---
.../gpu/drm/omapdrm/displays/encoder-tpd12s015.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
b/drivers/gpu/drm/oma
This patch adds documentation of device tree bindings for the
Synopsys DesignWare MIPI DSI host DRM bridge driver.
Signed-off-by: Philippe CORNU
---
.../bindings/display/bridge/dw_mipi_dsi.txt| 30 ++
1 file changed, 30 insertions(+)
create mode 100644
Documentation
Signed-off-by: Geert Uytterhoeven
Acked-by: Rob Herring
---
v3:
- No changes,
v2:
- Add Acked-by.
---
arch/powerpc/boot/dts/acadia.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/acadia.dts b/arch/powerpc/boot/dts/acadia.dts
index 57291f61ffe702
Fixes: fd913ef7ce619467 ("Bluetooth: btusb: Add out-of-band wakeup support")
Signed-off-by: Geert Uytterhoeven
---
v3:
- New.
---
Documentation/devicetree/bindings/net/btusb.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/btusb.txt
The HDMI controller in the A31 SoC is slightly different from the
earlier version. In addition to the TMDS clock and DDC controls,
this version now takes a second DDC clock input.
Add a compatible string for it, and add the DDC clock input to the
list of clocks required.
Signed-off-by: Chen-Yu Ts
Add heuristic to decide that AUX or PWM pin should use for
backlight brightness adjustment and modify i915 param description
to have auto, force disable, and force enable.
The heuristic to determine that using AUX pin is better than using
PWM pin is that the panel support any of the feature list h
Add the panel-bridge support for both panels & bridges (used by DSI host &
HDMI/LVDS bridges).
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/stm/Kconfig | 2 +-
drivers/gpu/drm/stm/ltdc.c | 208 +++-
drivers/gpu/drm/stm/ltdc.h | 2 +-
3 files cha
Add the STM32 DSI host driver that uses the Synopsys DesignWare
MIPI DSI DRM bridge.
Signed-off-by: Philippe CORNU
---
drivers/gpu/drm/stm/Kconfig | 8 +
drivers/gpu/drm/stm/Makefile | 2 +
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 353 ++
3 f
On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:
Somehow the CC's got removed in my previous reply, adding them back. See
one additional comment below.
> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > Add heuristic to decide that AUX or PWM pin should use for
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravoot
On Sat, Jun 3, 2017 at 3:30 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
>> The DDC parent clock on the A31 SoC is also conveniently named
>> "hdmi-ddc", which results in a name collision when the hdmi driver
>> registers its internal DDC divider clock.
Hello,
We're observing the following build failure with v4.12-rc3, latest
linux.git and linux-next.git:
[ 9825s] LD vmlinux.o
[ 9904s] MODPOST vmlinux.o
[ 9915s] drivers/built-in.o: In function `hdmi_get_modes':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/lin
This patch adds documentation of device tree bindings for the STM32
DSI host driver based on the Synopsys DW MIPI DSI bridge driver.
---
.../devicetree/bindings/display/st,stm32-ltdc.txt | 83 +-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/Documentation/devic
This patch adds option to enable dynamic backlight for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Change-Id: I52f04b814bb4cd9df570ab59094ae974b9baec5b
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/d
Hi Emil!
On Fri, Jun 2, 2017 at 1:14 PM, Emil Velikov wrote:
> As Daniel mentioned in the earlier thread, factoring out things can be
> done as a follow-up.
> On the other hand, I _think_ that the blocker for this driver that
> it's not doing atomic mode setting.
>
I've been looking on other sma
-HOST/20170603-231124
base: git://people.freedesktop.org/~airlied/linux.git drm-next
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross
https://bugs.freedesktop.org/show_bug.cgi?id=98145
--- Comment #7 from Klaus Kusche ---
(In reply to Henri Kemppainen from comment #5)
> Created attachment 131597 [details] [review]
> disable gtf modes
Patch works perfectly:
* The beamers are now auto-configuring the correct mode on startup,
wi
https://bugs.freedesktop.org/show_bug.cgi?id=101290
Bug ID: 101290
Summary: Radeon R9 390X regression - No output (CVT) or
corruption (CVT-R) at 4096x2160@60Hz over DisplayPort
Product: DRI
Version: unspecified
Hardware: Ot
Hi,
On 06/02/2017 05:34 PM, Boris Brezillon wrote:
Document the bindings used for the Cadence DSI bridge.
Signed-off-by: Boris Brezillon
---
.../bindings/display/bridge/cdns,dsi.txt | 55 ++
1 file changed, 55 insertions(+)
create mode 100644
Documentation/devi
On 6/2/2017 5:34 PM, Boris Brezillon wrote:
Add a driver for Cadence DPI -> DSI bridge.
Signed-off-by: Boris Brezillon
---
Changes in v2:
- rebase on v4.12-rc1 and adapt to driver to the drm_bridge API changes
- return the correct error when devm_clk_get(sysclk) fails
- add missing depends on
https://bugs.freedesktop.org/show_bug.cgi?id=101294
Bug ID: 101294
Summary: radeonsi minecraft forge splash freeze since 17.1
Product: Mesa
Version: 17.1
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
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