On Wed, May 17, 2017 at 08:55:08AM +0200, Michal Hocko wrote:
> From: Michal Hocko
>
> drm_[cm]alloc* has grown their own kvmalloc with vmalloc fallback
> implementations. MM has grown kvmalloc* helpers in the meantime. Let's
> use those because it a) reduces the code and b) MM has a better idea
Both TCON channels need to have the resolution doubled, since the size the
hardware is going to use is whatever we put in the register divided by two.
However, we handle it differently for the two channels: in the channel 0,
our register access macro does the multiplication of the value passed as
So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.
This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.
Clocks
Hi,
Here is an attempt at getting the HDMI controller running.
This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s,
A20, A31).
This driver only supports for now the A10s because it was an easy target,
being very close to the A13 that is already supported by our DRM driver.
The current function name is a bit confusing, and doesn't really allow to
create an explicit function to reverse the operation.
We also for now change the parent rate through a pointer, while we don't
return anything.
In order to be less confusing, and easier to use for downstream users,
change t
The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_d
The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.
However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that migh
divider_round_rate_parent already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_div.c | 27 ---
1 file changed, 4
It seems like what's called a backporch in the datasheet is actually the
backporch plus the sync period. Fix that in our driver.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dri
The pre-divider retrieval code was merged into the function to apply the
current pre-divider onto the parent clock rate so that we can use that
adjusted value to do our factors computation.
However, since we'll need to do the reverse operation, we need to split out
that code into a function that w
Even though that mux is undocumented, it seems like it needs to be set to 1
when using composite, and 0 when using HDMI.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/driver
The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun5i.h | 6 --
include/dt-bindings/clock/sun5i-ccu.h | 3 +++
2 files changed, 7 insertions(+),
Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.
This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previ
One of the possible output of the display pipeline, on the SoCs that have
it, is the HDMI controller.
Add a binding for it.
Acked-by: Chen-Yu Tsai
Acked-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 79 +++-
1 file changed
The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
controller.
That HDMI controller is able to do audio and CEC, but those have been left
out for now.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Kconfig | 9 +-
drivers/gp
The generic connectors such as hdmi-connector doesn't have any driver in,
so if they are added to the component list, we will be waiting forever for
a non-existing driver to probe.
Add a list of the connectors we want to ignore when building our component
list.
Signed-off-by: Maxime Ripard
---
The muxing can actually happen on both channels on some SoCs, so it makes
more sense to just move it out of the sun4i_tcon1_mode_set function and
create a separate function that needs to be called by the encoders.
Let's do that and convert the existing drivers.
Signed-off-by: Maxime Ripard
Acked
The A10s has an HDMI controller connected to the second TCON channel. Add
it to our DT.
Since the TV Encoder was the only channel 1 user so far, also add the
property now that we have several users.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 47
The A10s Olinuxino has an HDMI connector. Make sure we can use it.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 +-
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b
The A10s has a slightly different display pipeline than the A13, with an
HDMI controller.
Add a compatible for it.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
2 files c
While all functions have debug logs, the channel enable and disable are not
logged. Make sure this is the case.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
It appears that the total vertical resolution needs to be doubled when
we're not in interlaced. Make sure that is the case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/g
The Allwinner Timings Controller has two, mutually exclusive, channels.
When the binding has been introduced, it was assumed that there would be
only a single user per channel in the system.
While this is likely for the channel 0 which only connects to LCD displays,
it turns out that the channel 1
struct omap_drm_window is only used to pass plane setup data to
omap_framebuffer_update_scanout(). This can as well be accomplished by
just passing the DRM state.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_drv.h | 11 +--
drivers/gpu/drm/omapdrm/omap_fb.c| 35 ++
Change dispc driver to use the DRM_REFLECT flags instead of a mirror
boolean.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 24 ++--
drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 --
drivers/gpu/drm/omapdrm/omap_plane.c | 1 -
3 files changed, 10 in
Hi,
This series cleans up rotation related code and fixes the major bugs with
rotation with YUV422 pixelformats. This series is based on the earlier
"drm/omap: misc cleanups and pixel format change" series.
There are still some smaller bugs with the rotation when used with scaling,
which I will c
At the moment the dispc driver uses a custom enum for rotation. Change
it to use the DRM's DRM_ROTATE_*.
Note that mirroring is at the moment handled as a separate boolean in
the dispc driver, so we only use the DRM_ROTATE_* values.
Note, DSS HW uses clockwise rotation, DRM counter-clockwise.
Si
The omapdrm driver has not passed the rotation value to the dispc
driver. This doesn't affect RGB formats, but YUV formats don't work
without dispc knowing the orientation.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_fb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/d
When rotating 90/270 + mirroring with YUV422, the end result will have
adjacent pixels swapped. The problem is that
dispc_ovl_set_rotation_attrs() has wrong rotation values for these
cases.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 4 ++--
1 file changed, 2 insertio
Add a helper function to convert DRM rotation to TILER rotation.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_fb.c | 56 ++-
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/
TILER rotation with YUV422 pixelformats does not work at the moment. All
other pixel formats work, because the pixelformat's pixel size is equal
to tiler unit size (e.g. XR24's pixel size is 32 bits, and the TILER
unit size that has to be used is 32 bits).
For YUV422 formats this is not the case,
On Wed, May 17, 2017 at 09:44:53AM +0200, Michal Hocko wrote:
> On Tue 16-05-17 12:09:08, Chris Wilson wrote:
> > On Tue, May 16, 2017 at 12:53:52PM +0200, Michal Hocko wrote:
> > > On Tue 16-05-17 10:31:19, Chris Wilson wrote:
> > > > On Tue, May 16, 2017 at 11:06:06AM +0200, Michal Hocko wrote:
>
Currently, the duplicated sg table is freed in the detach() and
the error path of map_dma_buf() ion's dma_buf_ops.
If a call to dma_buf_map_attachment() fails, the importer is
expected to call dma_buf_detach() to remove the attachment. This
will result in us trying to free the duped sg table twice
A few members in ion_buffer struct are unused after features
like page faulting, ion_handle and ion_client were removed.
Remove these members and the leftover references to them.
Signed-off-by: Archit Taneja
---
drivers/staging/android/ion/ion.c | 2 --
drivers/staging/android/ion/ion.h | 14 --
The recent ION clean ups introduced some leftover code that can be
removed, and a bug that comes up if the call to dma_buf_map_attachment()
from an importer fails. Fix these.
Archit Taneja (3):
staging: android: ion: Remove unused members from ion_buffer
staging: android: ion: Remove ION_FLAG_
The flag ION_FLAG_CACHED_NEEDS_SYNC isn't used anymore. Remove it.
Signed-off-by: Archit Taneja
---
drivers/staging/android/uapi/ion.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/staging/android/uapi/ion.h
b/drivers/staging/android/uapi/ion.h
index b76db1b2e197..d415589757e
Am 17.05.2017 um 04:20 schrieb Gustavo A. R. Silva:
Local variable _color_ is assigned to a constant value and it is
never updated again. Remove this variable and refactor the code it
affects.
Addresses-Coverity-ID: 1226745
Signed-off-by: Gustavo A. R. Silva
Mhm, on the one hand it looks like
Am 16.05.2017 um 23:11 schrieb Lyude:
This is the first part of me going through and cleaning up the IRQ handling
code for radeon, since after taking a look at it the other day while trying to
debug something I realized basically all of the code was copy pasted
everywhere, and quite difficult to
https://bugs.freedesktop.org/show_bug.cgi?id=101029
--- Comment #14 from Michel Dänzer ---
Looks like https://patchwork.freedesktop.org/patch/146519/ might help, or
passing iommu=soft on the kernel command line might serve as a workaround.
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On Wed, May 17, 2017 at 11:03:50AM +0200, Michal Hocko wrote:
> On Wed 17-05-17 08:38:09, Chris Wilson wrote:
> > On Wed, May 17, 2017 at 08:55:08AM +0200, Michal Hocko wrote:
> > > From: Michal Hocko
> > >
> > > drm_[cm]alloc* has grown their own kvmalloc with vmalloc fallback
> > > implementati
https://bugs.freedesktop.org/show_bug.cgi?id=100510
Arthur Marsh changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|FIXED
Hi Dave,
just a single fix for a refcounting issue, introduced with the new
explicit fencing support in 4.12.
Regards,
Lucas
The following changes since commit 8b03d1ed2c43a2ba5ef3381322ee4515b97381bf:
Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next
(2017-05-02 04:4
On Fri, 30 Dec 2016, Daniel Vetter wrote:
> On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
>> Several DRM drivers print the same initialization message right after
>> drm_dev_register, so move that to common code. The exception is i915,
>> which uses its own register han
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
> This is the plumbing for supporting fb modifiers on planes. Modifiers
> have already been introduced to some extent, but this series will extend
> this to allow querying modifiers per plane. Based on this, the client to
> enable optima
error log:
xf86drm.c: In function 'parse_separate_sysfs_files':
xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed in
C99 mode
for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
^
xf86drm.c:3104:5: note: use option -std=c99 or -std=gnu99 to co
Hi Michal,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.12-rc1 next-20170517]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michal-Hocko/drm-replace-drm_-cm-alloc-by
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
> On 17-05-03 17:08:27, Daniel Vetter wrote:
> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > > +struct drm_format_modifier_blob {
> > > +#define FORMAT_BLOB_CURRENT 1
> > > + /* Version of this blob format */
> > >
On Wed, May 17, 2017 at 10:56:25AM +0530, Archit Taneja wrote:
> Hi,
>
> On 05/16/2017 08:14 PM, Archit Taneja wrote:
> >
> >
> > On 5/13/2017 12:40 AM, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > Add support to async updates of cursors by using the new atomic
> > > interfac
On Wed, May 17, 2017 at 01:06:46PM +0300, Jani Nikula wrote:
> On Fri, 30 Dec 2016, Daniel Vetter wrote:
> > On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
> >> Several DRM drivers print the same initialization message right after
> >> drm_dev_register, so move that to co
On Wed, 17 May 2017, Daniel Vetter wrote:
> On Wed, May 17, 2017 at 01:06:46PM +0300, Jani Nikula wrote:
>> On Fri, 30 Dec 2016, Daniel Vetter wrote:
>> > On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
>> >> Several DRM drivers print the same initialization message right
On Mon, Apr 24, 2017 at 01:50:33PM +0900, Masahiro Yamada wrote:
> Include instead of relative path from include/drm, then
> remove the -Iinclude/drm compiler flag.
>
> While we are here, use <...> instead of "..." for include/linux/*.h
> headers too.
>
> Signed-off-by: Masahiro Yamada
This on
https://bugs.freedesktop.org/show_bug.cgi?id=101029
--- Comment #15 from Craig ---
where do i find the amd_iommu.c in ubuntu 17.04 so that I can patch it? or is
there a different method? I was considering using this syntax: patch -p[num] <
patchfile
patch [options] originalfile patchfile
thanks v
https://bugs.freedesktop.org/show_bug.cgi?id=101029
--- Comment #16 from Craig ---
(In reply to Craig from comment #15)
> where do i find the amd_iommu.c in ubuntu 17.04 so that I can patch it? or
> is there a different method? I was considering using this syntax: patch
> -p[num] < patchfile
> pa
https://bugs.freedesktop.org/show_bug.cgi?id=100577
--- Comment #7 from Harry Wentland ---
This might've been fixed by Mario's patches plus Andrey's scanline change
d58f8724e636 Mario Kleiner
drm/amd/display: Prevent premature pageflip when comitting in vblank. (v3)
8494f61e14ff Mario Klei
Hi Qiang Yu,
On 17 May 2017 at 10:26, Qiang Yu wrote:
> error log:
> xf86drm.c: In function 'parse_separate_sysfs_files':
> xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed in
> C99 mode
> for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
>
Hi Emil,
I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure pass
but
fail when compile.
I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
configure
script add it into CC variable. When just use "make", it's OK, but my build
script uses
"make CC
https://bugs.freedesktop.org/show_bug.cgi?id=100437
--- Comment #7 from Corbin ---
Same error as well.
System Specs :
Gentoo Linux x86_64, Kernel 4.9.x
AMDGPU v1.2 Driver
AMD 990FX Chipset
AMD FX-9590 CPU
AMD RX480 Video Card
AMDGPU Firmware blobs compiled into the kernel.
GART IOMMU support not
New version of [1] with DPCD OUI etc. reading moved from i915 to DP
helpers, and the quirks based on that. Helps improve the documentation
that Daniel longed for.
BR,
Jani.
[1] 20170511095721.7392-1-jani.nikula@intel.com">http://mid.mail-archive.com/20170511095721.7392-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 35 +++
include/drm/drm_dp_helper.h | 19 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3e5f52110ea1..
Switch to using the common DP helpers instead of using our own.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 37 -
drivers/gpu/drm/i915/intel_drv.h| 5 +
drivers/gpu/drm/i915/intel_lspcon.c | 2 +-
3 files changed, 6 insertion
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on the DP device
identification. At least
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
v3 by Jani: Rebased on the reworked DP quirk database
Fixes: 9a86cda07af2 ("
Hey Ville,
On 2017-05-16 12:20 PM, Ville Syrjälä wrote:
On Tue, May 16, 2017 at 11:55:00AM -0400, Robert Foss wrote:
Add DRM_ROTATE_ and DRM_REFLECT_ defines to the UAPI as a convenience.
I just noticed this line using the wrong define names.
Will fix in v3.
Ideally the DRM_ROTATE_ and DRM
https://bugs.freedesktop.org/show_bug.cgi?id=100510
Michel Dänzer changed:
What|Removed |Added
Resolution|--- |FIXED
Status|REOPENED
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switc
On Wed, May 17, 2017 at 1:31 PM, Daniel Vetter wrote:
> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
>> On 17-05-03 17:08:27, Daniel Vetter wrote:
>> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
>> > > +struct drm_format_modifier_blob {
>> > > +#define FORMAT_BL
On 17 May 2017 at 14:58, Yu, Qiang wrote:
> Hi Emil,
>
> I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure
> pass but
> fail when compile.
>
> I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
> configure
> script add it into CC variable. When j
On 05/17/2017 01:15 AM, Archit Taneja wrote:
> The recent ION clean ups introduced some leftover code that can be
> removed, and a bug that comes up if the call to dma_buf_map_attachment()
> from an importer fails. Fix these.
>
> Archit Taneja (3):
> staging: android: ion: Remove unused members
On Wed, May 17, 2017 at 10:47:16PM +0800, Icenowy Zheng wrote:
> This patchset is the initial patchset for Allwinner DE2 support.
>
> As the DE2 CCU support is already applied, this patchset now contains
> only DRM changes and device tree changes.
>
> The SoC used to develop this patchset is V3s
2017-05-18 0:10 GMT+08:00 Emil Velikov :
> On 17 May 2017 at 14:58, Yu, Qiang wrote:
>> Hi Emil,
>>
>> I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure
>> pass but
>> fail when compile.
>>
>> I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
>>
From: Colin Ian King
The current for loop decrements i when it is zero and this causes
a wrap-around back to ~0 because i is unsigned. In the unlikely event
that mask is 0, the loop will run forever. Fix this so we can't loop
forever.
Detected by CoverityScan, CID#1435469 ("Unsigned compared aga
On Wednesday, 2017-05-17 13:58:42 +, Yu, Qiang wrote:
> Hi Emil,
>
> I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure
> pass but
> fail when compile.
>
> I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
> configure
> script add it into CC
Daniel Vetter writes:
> On Thu, Apr 20, 2017 at 09:38:19PM -0300, Gabriel Krisman Bertazi wrote:
>> While reading drm_for_each_connector_iter, I noticed a mention to
>> drm_connector_begin which doesn't exist. It should be
>> drm_connector_get.
>>
>> Signed-off-by: Gabriel Krisman Bertazi
>
> F
https://bugs.freedesktop.org/show_bug.cgi?id=97942
--- Comment #6 from Humberto Israel Perez Rodriguez
---
The following test cases failure on BXT with latest configuration
igt@gem_mmap@swap-bo
igt@gem_mmap_gtt@coherency
igt@gem_mmap_gtt@swap-copy
igt@gem_mmap_gtt@swap-copy-odd
igt@gem_mmap_gtt
https://bugs.freedesktop.org/show_bug.cgi?id=97942
Humberto Israel Perez Rodriguez changed:
What|Removed |Added
Summary|[IGT] [BYT] /gem_mmap_gtt |[IGT] [BYT] [BXT]
I sent a patch for this bug earlier. There is a second bug later in the
function which my patch fixes as well.
regards,
dan carpenter
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On 05/17/2017 07:25 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query b
On Wed, May 17, 2017 at 11:29:13PM +0200, Nicolai Stange wrote:
> Hi,
>
> my system (always) locks up when booting a next-20170515 kernel.
>
> No oops. Sending magic sysrqs over serial doesn't cause any reaction.
>
> Last few console messages before death are:
>
> [7.089221] Console: swit
https://bugs.freedesktop.org/show_bug.cgi?id=100577
--- Comment #8 from Andy Furniss ---
I can still reproduce this.
Seems I may just get lucky runs - one 90 mins no issue, stopped and started
again later and it locked after 20.
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Commit b60c1be74741 (dt-bindings: display/panel: Add common rotation property)
added the rotation property description in a new file. We have a place for
common display panel properties already. Move there the rotation property.
Cc: Noralf Trønnes
Cc: Rob Herring
Signed-off-by: Baruch Siach
---
On 16.05.2017 11:10, Mikko Perttunen wrote:
>
>
> On 16.05.2017 10:32, Erik Faye-Lund wrote:
>> On Tue, May 16, 2017 at 8:56 AM, Mikko Perttunen wrote:
>>> On 14.05.2017 23:47, Dmitry Osipenko wrote:
If commands buffer claims a number of words that is higher than its BO can
fit, a
On Tue 16-05-17 15:08:56, Daniel Vetter wrote:
> On Tue, May 16, 2017 at 11:52:55AM +0200, Michal Hocko wrote:
> > On Tue 16-05-17 11:22:30, Daniel Vetter wrote:
> > > On Tue, May 16, 2017 at 11:06:06AM +0200, Michal Hocko wrote:
> > > > From: Michal Hocko
> > > >
> > > > drm_malloc* has grown th
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency divisor is still
within 25% of the desired value.
Signed-off-by: Puthikorn V
On Wed 17-05-17 10:12:41, Chris Wilson wrote:
> On Wed, May 17, 2017 at 11:03:50AM +0200, Michal Hocko wrote:
[...]
> > +static inline bool alloc_array_check(size_t n, size_t size)
> > +{
> > + if (size != 0 && n > SIZE_MAX / size)
> > + return false;
> > + return true;
>
> Just retu
On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat wrote:
> >
> >
> > On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran
> > wrote:
> > On Tue, 2017-05-16 at 11:07 -0700, Puthikorn Vo
On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Tue, 2017-05-16 at 11:07 -0700, Puthikorn Voravootivat wrote:
> >
> >
> > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran
> > wrote:
> > On Mon, 2017-05-15 at 17:43 -0700, Puthikorn V
Allwinner H3 features a "DE2.0" and a TV Encoder.
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- The connection between H3 TCONs and H3 Mixers
- H3 TV Encoder
- H3 Display engine
Signed-off-by: Icenowy Zheng
---
.../bindings/display/sunxi/sun4i-drm.txt | 47
On Wed, May 17, 2017 at 3:40 PM, Maxime Ripard
wrote:
> The A10s has a slightly different display pipeline than the A13, with an
> HDMI controller.
>
> Add a compatible for it.
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
___
dri-devel m
This patchset is the initial patchset for Allwinner DE2 support.
As the DE2 CCU support is already applied, this patchset now contains
only DRM changes and device tree changes.
The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs that have DE2.
(Allwinner V3s fea
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI.
Add support for these two variants.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
1 file changed, 18 insertions(+)
dif
On Wed, May 17, 2017 at 3:40 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
> 1 fi
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insert
This patchset depends on the DE2 patchset, version 8 of that patchset
is available at [1].
Allwinner H3 SoC features a TV Encoder like the one in Allwinner A13,
which can only output TV Composite signal.
The display pipeline of H3 is also special -- it has two mixers and
two TCONs, of which the c
As it turned out my allyesconfig on x86_64 wasn't sufficient and 0day
build machinery found a failure on arm architecture. It was clearly a
typo. Now I have pushed this to my build battery with cross arch
compilers and it passes so there shouldn't more surprises hopefully.
Here is the v2.
---
From
Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.
Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.
So allow CLK_DE to set CLK_P
There are some panel that
(1) does not support display backlight enable via AUX
(2) support display backlight adjustment via AUX
(3) support display backlight enable via eDP BL_ENABLE pin
The current driver required that (1) must be support to enable (2).
This patch drops that requirement.
Signed
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.
Add device nodes for this display pipeline.
Signed-off-by: Icenowy Zheng
---
Changes in v8:
- Changed some label names.
Changes in v7:
- Change DE2 clock co
On Tue, 2017-05-16 at 17:39 -0700, Puthikorn Voravootivat wrote:
>
>
> On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran
> wrote:
> On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat
> wrote:
> >
> >
> > On Tue, May 16, 2017 at 1:29 PM, Pandiyan
On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat wrote:
> >
> >
> > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, Dhinakaran
> > wrote:
> > On Fri, 2017-05-12 at 17:31 -0700, Puthikorn V
在 2017-05-15 17:24,Maxime Ripard 写道:
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ? (See A80 DTSI)
+ comp
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