https://bugs.freedesktop.org/show_bug.cgi?id=99955
Hleb Valoshka <375...@gmail.com> changed:
What|Removed |Added
CC||375...@gmail.com
--- C
https://bugs.freedesktop.org/show_bug.cgi?id=98856
Gregor Münch changed:
What|Removed |Added
Summary|[Regression, SI] DIRT: |DIRT: Showdown broken
|
https://bugs.freedesktop.org/show_bug.cgi?id=98856
--- Comment #8 from Gregor Münch ---
Created attachment 130076
--> https://bugs.freedesktop.org/attachment.cgi?id=130076&action=edit
garbled graphics #1
Found the problem. Seems like using -Ofast wasnt a good idea. Using -03
everything works a
https://bugs.freedesktop.org/show_bug.cgi?id=100067
Bug ID: 100067
Summary: [OpenCL] const int in argument list crashes build
Product: Mesa
Version: 17.0
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
https://bugs.freedesktop.org/show_bug.cgi?id=100068
Bug ID: 100068
Summary: LLVM ERROR: Cannot select: intrinsic
%llvm.amdgcn.buffer.load.format
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux
https://bugs.freedesktop.org/show_bug.cgi?id=100070
Bug ID: 100070
Summary: Rocket League: grass gets rendered incorrectly
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
https://bugs.freedesktop.org/show_bug.cgi?id=100068
Dave Airlie changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=97988
--- Comment #29 from Kai ---
Ping.
@nha: is there any progress on this? Or more specifically the LLVM change
D26348?
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https://bugs.freedesktop.org/show_bug.cgi?id=100071
Bug ID: 100071
Summary: [Regression] Tomb Raider: TressFX broken with recent
LLVM
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NE
https://bugs.freedesktop.org/show_bug.cgi?id=100068
--- Comment #2 from Wojciech Pyczak ---
Created attachment 130081
--> https://bugs.freedesktop.org/attachment.cgi?id=130081&action=edit
Unigine Heaven output
Looks like it's not all, glxgears works fine though.
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Hi Kieran,
Thank you for the patch.
On Sunday 05 Mar 2017 16:00:03 Kieran Bingham wrote:
> To be able to perform page flips in DRM without flicker we need to be
> able to notify the rcar-du module when the VSP has completed its
> processing.
>
> We must not have bidirectional dependencies on the
Hi Kieran,
Thank you for the patch.
On Sunday 05 Mar 2017 16:00:02 Kieran Bingham wrote:
> If we try to commit the display list while an update is pending, we have
> missed our opportunity. The display list manager will hold the commit
> until the next interrupt.
>
> In this event, we skip the p
Hi Kieran,
Thank you for the patch.
On Sunday 05 Mar 2017 16:00:04 Kieran Bingham wrote:
> Currently we process page flip events on every display interrupt,
> however this does not take into consideration the processing time needed
> by the VSP1 utilised in the pipeline.
>
> Register a callback
Hi Maxime,
On Tue, Feb 28, 2017 at 04:36:51PM +0100, Maxime Ripard wrote:
> Implement legacy framebuffer ioctl FBIO_WAITFORVSYNC in the generic
> framebuffer emulation driver. Legacy framebuffer users like non kms/drm
> based OpenGL(ES)/EGL implementations may require the ioctl to
> synchronize dr
Hi!
> > mplayer stopped working after a while. Dmesg says:
> >
> > [ 3000.266533] cdc_ether 2-1.2:1.0 usb0: register 'cdc_ether' at
Now I'm pretty sure it is a regression in v4.11-rc0. Any ideas what to
try? Bisect will be slow and nasty :-(.
The PHY requires us to wait for the PHY to switch to low power mode
after deasserting TXPWRON and before asserting PDDQ in the power down
sequence, otherwise power down will fail.
The PHY power down can be monitored though the TX_READY bit, available
through I2C in the PHY registers, or the TX_PHY
When powering the PHY up we need to wait for the PLL to lock. This is
done by polling the TX_PHY_LOCK bit in the HDMI_PHY_STAT0 register
(interrupt-based wait could be implemented as well but is likely
overkill). The bit is asserted when the PLL locks, but the current code
incorrectly waits for the
The HDMI TX controller support different PHYs whose programming
interface can vary significantly, especially with vendor PHYs that are
not provided by Synopsys. To support them, create a PHY operation
structure that can be provided by the platform glue layer. The existing
PHY handling code (limited
Retrieve the LVDS mode from the panel and configure the LVDS encoder
accordingly. LVDS mode selection is static as LVDS panels can't be
hot-plugged on any of the device supported by the driver. Support for
dynamic mode selection can be implemented in the future when needed.
Signed-off-by: Laurent
When a DT node connected to a DU output is disabled no bridge will ever
be instantiated for it. Skip the output in that case.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
Instead of parsing the panel device tree node manually, use the panel
API to delegate panel handling to a panel driver.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 1 +
drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 22 ++
drivers/gpu/drm/rcar-du/rcar_du
From: Koji Matsuoka
The R-Car Gen3 SoCs include on-chip DesignWare HDMI encoders. Support
them with a platform driver to provide platform glue data to the dw-hdmi
driver.
The driver is a complete rewrite of code coming from the Renesas BSP,
save for the values in the PHY parameters table.
Signe
Hello,
This patch series implements support for the HDMI output on Renesas R-Car Gen3
SoCs, and more specifically on the R-Car H3.
Compared to the previous version, I've left out all the dw-hdmi patches that
have been updated separately and are on their way to being merged. I've also
left out the
The Renesas R-Car Gen3 SoCs use a Synopsys DWC HDMI TX encoder IP. Add
corresponding device tree bindings based on the DWC HDMI TX bindings
model.
Signed-off-by: Laurent Pinchart
Acked-by: Rob Herring
---
.../bindings/display/bridge/renesas,dw-hdmi.txt| 75 ++
MAINTAINER
The rcar-du driver contains a manual implementation of HDMI and VGA
bridges. Use DRM bridges to replace it.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/Kconfig | 6 --
drivers/gpu/drm/rcar-du/Makefile | 5 +-
drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 104
Unlike the connector type, the encoder type is unused by userspace. As
it is equally unused in the driver, except in a single location where
the connector type can be used instead, hardcode it to
DRM_MODE_ENCODER_NONE. This allow removing all code that tries to
determine (unsuccessfully in case a b
From: Koji Matsuoka
Update the device description with the two available HDMI outputs.
Signed-off-by: Koji Matsuoka
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 4 +++-
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 12 ++--
2 files changed, 13 insertions(+)
From: Koji Matsuoka
The implementation hardcodes a workaround for the H3 ES1.x SoC
regardless of the SoC revision, as the workaround can be safely applied
on all devices in the Gen3 family without any side effect.
Signed-off-by: Koji Matsuoka
Signed-off-by: Ulrich Hecht
Signed-off-by: Laurent
* Sebastian Reichel [170304 16:45]:
> Signed-off-by: Sebastian Reichel
> [t...@atomide.com: rebased on event_lock changes]
So for this feel free to add:
Tested-by: Tony Lindgren
Signed-off-by: Tony Lindgren
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On Tue, Feb 28, 2017 at 03:28:10PM +0100, Peter Senna Tschudin wrote:
> Devicetree binding documentation for the second video output
> of the GE B850v3:
>STDP4028-ge-b850v3-fw bridges (LVDS-DP)
>STDP2690-ge-b850v3-fw bridges (DP-DP++)
>
> Added entry for MegaChips at:
> Documentation/devi
On March 03, 2017 5:45 AM Laura Abbott wrote:
>
> +static struct sg_table *dup_sg_table(struct sg_table *table)
> +{
> + struct sg_table *new_table;
> + int ret, i;
> + struct scatterlist *sg, *new_sg;
> +
> + new_table = kzalloc(sizeof(*new_table), GFP_KERNEL);
> + if (!new_
This change adopts debugfs usage for outputting useful data.
As of today we print:
* Mode and real HW clock values
* Standard FB info
Code is heavily borrowed from ARM's HDLCD thus adding Liviu in Cc.
Signed-off-by: Alexey Brodkin
Cc: Liviu Dudau
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jose
* Sebastian Reichel [170304 16:45]:
> The N950's display requires two regulators.
Also needed for droid 4:
Tested-by: Tony Lindgren
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To be able to perform page flips in DRM without flicker we need to be
able to notify the rcar-du module when the VSP has completed its
processing.
We must not have bidirectional dependencies on the two components to
maintain support for loadable modules, thus we extend the API to allow
a callback
This adds support for the Winstar Display Co. WF35LTIACD 3.5" QVGA TFT
LCD panel, which can be supported by the simple panel driver.
Signed-off-by: Richard Genoud
---
.../bindings/display/panel/winstar,wf35ltiacd | 7 ++
drivers/gpu/drm/panel/panel-simple.c | 28 +
Winstar Display Corp. is specialized in LCD displays for embedded
products.
cf: http://www.winstar.com.tw
Signed-off-by: Richard Genoud
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.
* Sebastian Reichel [170304 16:45]:
> Save the framedone callback supplied by dss for later
> usage.
>
> Signed-off-by: Sebastian Reichel
Tested-by: Tony Lindgren
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On Fri, Mar 03, 2017 at 11:39:45AM +, John Keeping wrote:
> This reset is required in order to fully reset the internal state of the
> MIPI controller.
>
> Signed-off-by: John Keeping
> ---
> On Thu, 2 Mar 2017 13:56:46 -0800, Brian Norris wrote:
> > On Fri, Feb 24, 2017 at 12:55:06PM +,
Hi Jose,
On Fri, 2017-03-03 at 18:05 +, Jose Abreu wrote:
> Hi Alexey,
>
>
> On 03-03-2017 13:27, Alexey Brodkin wrote:
> >
> >
> > So if I understood you correct here what I really need is just to get rid
> > of existing check,
> > right? I.e. the following is to be in v2 respin:
> > ---
Hi Laurent,
On 03-03-2017 16:50, Laurent Pinchart wrote:
> The driver is already made of 5 separate source files. Move it to a
> newly created directory named synopsys where more Synopsys bridge
> drivers can be added later (for the DisplayPort controller for
> instance).
>
> Suggested-by: Jose A
On Thu 02-03-17 13:44:32, Laura Abbott wrote:
> Hi,
>
> There's been some recent discussions[1] about Ion-like frameworks. There's
> apparently interest in just keeping Ion since it works reasonablly well.
> This series does what should be the final clean ups for it to possibly be
> moved out of s
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format.
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits
per channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixe
Hi Neil,
On 03-03-2017 16:42, Neil Armstrong wrote:
>
> Sure, I was meaning the *input* format the controller receives from the
> pixel encoder, I'm quite sure the format is strict.
>
Hmm, not quite following you here. As far as the controller goes
it supports the formats I mentioned:
-8
The rockchip use a special pixel format for those yuv pixel
format with 10 bits color depth.
Signed-off-by: Randy Li
---
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 1 +
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 34 ++---
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
Hi Neil,
On 03-03-2017 11:31, Neil Armstrong wrote:
>
> Sure, but I was struggling about finding an equivalence.
>
> How should I replace these ?
>
> DW_HDMI_ENC_FMT_RGB
> DW_HDMI_ENC_FMT_YCBCR444
> DW_HDMI_ENC_FMT_YCBCR422_16BITS
> DW_HDMI_ENC_FMT_YCBCR422_8BITS
> DW_HDMI_ENC_FMT_XVYCC444
>
> I
The formats added by this patch are:
V4L2_PIX_FMT_P010
V4L2_PIX_FMT_P010M
V4L2_PIX_FMT_P016
V4L2_PIX_FMT_P016M
Currently, none of driver uses those format.
Also a variant of V4L2_PIX_FMT_P010M pixel format is added.
The V4L2_PIX_FMT_P010CM is a compat variant of the
Document the optional properties for describing module resets, to
support resetting display channels and LVDS encoders on R-Car Gen2 and
Gen3.
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/display/renesas,du.txt | 10 ++
1 file changed, 10 insertions(+)
diff --
If we try to commit the display list while an update is pending, we have
missed our opportunity. The display list manager will hold the commit
until the next interrupt.
In this event, we inform the vsp1 completion callback handler so that
the du will not perform a page flip out of turn.
Signed-of
Devicetree binding documentation for the second video output
of the GE B850v3:
STDP4028-ge-b850v3-fw bridges (LVDS-DP)
STDP2690-ge-b850v3-fw bridges (DP-DP++)
Added entry for MegaChips at:
Documentation/devicetree/bindings/vendor-prefixes.txt
Cc: Laurent Pinchart
Cc: Martyn Welch
Cc: Mar
If we try to commit the display list while an update is pending, we have
missed our opportunity. The display list manager will hold the commit
until the next interrupt.
In this event, we skip the pipeline completion callback handler so that
the pipeline will not mistakenly report frame completion
From: Tony Lindgren
With manual mode displays we need to flush the panel manually.
Let's add flushing so we get Tomi's fbtest, kmstest, kmstest --flip,
and X and wayland working.
Signed-off-by: Tony Lindgren
[On Nokia N950]
Tested-By: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/omap_crtc.c
Hi Laurent,
Thanks for the review,
On 03/03/17 01:57, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Wednesday 01 Mar 2017 13:12:54 Kieran Bingham wrote:
>> The DRM object does not register the pipe with the WPF object. This is
>> used internally throughout the driver
Save the framedone callback supplied by dss for later
usage.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c
b/drivers/gpu/drm/omapdrm/omap_crtc.c
index b68
Currently we process page flip events on every display interrupt,
however this does not take into consideration the processing time needed
by the VSP1 utilised in the pipeline.
Register a callback with the VSP driver to obtain completion events, and
track them so that we only perform page flips wh
From: Tony Lindgren
Things are a bit whacked right now for panel-dsi-cm:
1. We're missing call to of_get_display_timing() and
videomode_from_timing()
2. We need to call dsicm_probe_of() after we initialize the
default values to not overwrite device tree configured
values
3. We need to
This reverts commit 5a35876e2830511cb8110667fc426c6a6165a593.
Revert the removal of manual update display support in
preparation for DSI command mode panels.
Signed-off-By: Sebastian Reichel
[t...@atomide.com: left out unused omap_framebuffer_dirty]
Signed-off-by: Tony Lindgren
---
drivers/gpu
From: Tony Lindgren
We can handle framedone interrupt directly simlar to commit
e0519af75d6e ("drm: omapdrm: Handle CRTC error IRQs directly").
By default we just print a warning on framedone and do nothing.
Any manually refreshed displays can register a callback.
Signed-off-by: Tony Lindgren
Signed-off-by: Sebastian Reichel
[t...@atomide.com: rebased and fixed up to work with droid 4]
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/omapdrm/omap_connector.c | 12 --
drivers/gpu/drm/omapdrm/omap_crtc.c | 65
drivers/gpu/drm/omapdrm/omap_drv.h
Add basic panel support for the Nokia N950. It must be tweaked a
little bit later, since the panel was built into the device
upside-down. Also the first 5 and the last 5 pixels are covered
by plastic.
Signed-off-By: Sebastian Reichel
---
arch/arm/boot/dts/omap3-n950.dts | 89
The RCAR-DU utilises a running VSPD pipeline to perform processing
for the display pipeline.
Changes to this pipeline are performed with an atomic flush operation which
updates the state in the VSPD. Due to the way the running pipeline is
operated, any flush operation has an implicit latency of on
The video processing pipeline on the second output on the GE B850v3:
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Each bridge has a dedicated flash containing firmware for supporting the
custom design. The result is that in this design neither the STDP4028
nor the ST
Hi Shashank,
On 03-03-2017 06:29, Shashank Sharma wrote:
> This patch does following:
> - Adds a new structure (drm_hdmi_info) in drm_display_info.
> This structure will be used to save and indicate if sink
> supports advanced HDMI 2.0 features
> - Adds another structure drm_scdc within drm_h
Hi Daniel,
On Thu, 2017-03-02 at 20:54 +0100, Daniel Vetter wrote:
> On Thu, Mar 02, 2017 at 08:27:54PM +0300, Alexey Brodkin wrote:
> >
> > Since we cannot always generate exactly requested pixel clock
> > there's not much sense in checking requested_clock == clk_round_rate().
> > In that case f
Configures the megachips-stdp-ge-b850v3-fw bridges on the GE
B850v3 dts file.
Cc: Laurent Pinchart
Cc: Martyn Welch
Cc: Martin Donnelly
Cc: Javier Martinez Canillas
Cc: Enric Balletbo i Serra
Cc: Philipp Zabel
Cc: Rob Herring
Cc: Fabio Estevam
Signed-off-by: Peter Senna Tschudin
---
U
Add MAINTAINERS entry for the second video output of the GE B850v3:
STDP4028-ge-b850v3-fw bridges (LVDS-DP)
STDP2690-ge-b850v3-fw bridges (DP-DP++)
Cc: Laurent Pinchart
Cc: Martyn Welch
Cc: Martin Donnelly
Cc: Daniel Vetter
Cc: Enric Balletbo i Serra
Cc: Philipp Zabel
Cc: Rob H
Signed-off-by: Sebastian Reichel
[t...@atomide.com: rebased on event_lock changes]
---
drivers/gpu/drm/omapdrm/dss/omapdss.h| 1 +
drivers/gpu/drm/omapdrm/dss/output.c | 6 ++
drivers/gpu/drm/omapdrm/omap_connector.c | 7 +++
drivers/gpu/drm/omapdrm/omap_crtc.c | 29 ++
Currently we process page flip events on every display interrupt,
however this does not take into consideration the processing time needed
by the VSP1 utilised in the pipeline.
Register a callback with the VSP driver to obtain completion events, and
track them so that we only perform page flips wh
To be able to perform page flips in DRM without flicker we need to be
able to notify the rcar-du module when the VSP has completed its
processing.
We must not have bidirectional dependencies on the two components to
maintain support for loadable modules, thus we extend the API to allow
a callback
* Sebastian Reichel [170304 16:45]:
> From: Tony Lindgren
>
> With manual mode displays we need to flush the panel manually.
>
> Let's add flushing so we get Tomi's fbtest, kmstest, kmstest --flip,
> and X and wayland working.
> --- a/drivers/gpu/drm/omapdrm/omap_crtc.c
> +++ b/drivers/gpu/drm/
Thanks to Clint's work, this version just correct some wrong info
in the comment.
I also offer a driver sample here, but it have been verified with
the 10 bits properly. I lacks of the userspace tool. And I am
not sure whether it is a properly way to support the pixel format
used in rockchip, alth
Hi Liviu,
On Fri, 2017-03-03 at 16:28 +, Liviu Dudau wrote:
> On Fri, Mar 03, 2017 at 06:19:24PM +0300, Alexey Brodkin wrote:
> >
> > - /* find the encoder node and initialize it */
> > - encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0);
> > - if (encoder_node) {
>
The RCAR-DU utilises a running VSPD pipeline to perform processing for the
display pipeline. This presents the opportunity for some race conditions to
affect the quality of the display output.
To prevent reporting page flips early, we must track this timing through the
VSP1, and only allow the rca
On Fri, Mar 03, 2017 at 09:22:06AM +0900, Andi Shyti wrote:
> Hi Hoegeun,
>
> > Hoegeun Kwon (7):
> > arm64: dts: exynos: Add the burst and esc clock frequency properties
> > for exynos5433 dts
> > arm: dts: Add the burst and esc clock frequency properties for
> > exynos3250 dts
> >
Hi Laurent,
On 02-03-2017 15:38, Laurent Pinchart wrote:
> Hi Jose,
>
> On Thursday 02 Mar 2017 14:50:02 Jose Abreu wrote:
>> On 02-03-2017 13:41, Laurent Pinchart wrote:
Hmm, this is kind of confusing. Why do you need a phy_ops and
then a separate configure_phy function? Can't we just
On Gen3 platforms compositing planes are allocated by VSP on behalf of
DRM/KMS.
If VSP support is not compiled in, vsp1 initialization stub routine is
called, leading to invalid memory accesses later on when un-initialized
planes are accessed.
Fail explicitly earlier if planes are not properly cr
Hi,
Some of you may remember, that I sent a series for the N950 display
some time ago. N950 has command mode DSI panel, so the main part of
the patchset takes care of adding manual display update support in
omapdrm.
The N950 also requires display rotation (the panel is mounted vertically
and bott
Hi Laurent,
On 03/03/17 02:11, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Wednesday 01 Mar 2017 13:12:55 Kieran Bingham wrote:
>> To be able to perform page flips in DRM without flicker we need to be
>> able to notify the rcar-du module when the VSP has completed it
The video processing pipeline on the second output on the GE B850v3:
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Each bridge has a dedicated flash containing firmware for supporting the
custom design. The result is that in this design neither the STDP4028
nor the ST
This is a workaround for a hardware bug occuring on OMAP3
with manually updated panels. Details about the HW bug are
unknown to me, but without this fix the panel refresh does
not work at all on Nokia N950.
Signed-off-By: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 2 ++
drive
Hi Phillip
$ git fetch https://git.pengutronix.de/git/pza/linux.git
tags/v4.10-ipu-dp-plane-fix
fatal: Not a git repository (or any of the parent directories): .git
I get the same error for:
git fetch https://git.pengutronix.de/git/pza/linux.git
tags/v4.10-ipu-dp-plane-fix
Thanks
On Mon, Feb
Hi Laurent,
On 03/03/17 02:17, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Wednesday 01 Mar 2017 13:12:56 Kieran Bingham wrote:
>> Updating the state in a running VSP1 requires two interrupts from the
>> VSP. Initially, the updated state will be committed - but only
Hi Laurent,
On 05/03/17 21:58, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Sunday 05 Mar 2017 16:00:03 Kieran Bingham wrote:
>> To be able to perform page flips in DRM without flicker we need to be
>> able to notify the rcar-du module when the VSP has completed its
>
Hello!
On 03/05/2017 07:00 PM, Kieran Bingham wrote:
Currently we process page flip events on every display interrupt,
however this does not take into consideration the processing time needed
by the VSP1 utilised in the pipeline.
Register a callback with the VSP driver to obtain completion eve
Hi Laurent,
在 2017年03月02日 06:39, Laurent Pinchart 写道:
Most of the hdmi_phy_test_*() functions are unused. Remove them.
Signed-off-by: Laurent Pinchart
Tested-by: Nickey Yang
Best regards,
Nickey Yang
---
drivers/gpu/drm/bridge/dw-hdmi.c | 26 --
1 file changed,
We used to use "encoder-slave" property in PGU's
Device Tree node to refer to the encoder, but since there's
a way to find it with some code smarts we get rid of
obviously extra complication in PGU node.
Again inspired by ARM's HDLCD code.
Signed-off-by: Alexey Brodkin
Cc: Liviu Dudau
Cc: Danie
On Gen3 platforms compositing planes are allocated by VSP on behalf of
DRM/KMS.
If VSP support is not compiled in, vsp initialization stub routine is
called. Return an error from that stub to fail explicitly, otherwise
accessing planes leads to invalid memory errors.
Signed-off-by: Jacopo Mondi
HI Laurent,
On 03/03/2017 12:26, Laurent Pinchart wrote:
Hi Jacopo,
Thank you for the patch.
On Friday 03 Mar 2017 09:09:38 Jacopo Mondi wrote:
On Gen3 platforms compositing planes are allocated by VSP on behalf of
DRM/KMS.
If VSP support is not compiled in, vsp1 initialization stub routine
I've finished doing the bulk of my house moving and have time to test
these patches now. I'm presuming they've not made it into 4.10(.1)
have they?
On Tue, Feb 28, 2017 at 2:18 PM, Philipp Zabel wrote:
> From: Lucas Stach
>
> This has never worked properly, as the IRQ got retriggered immediately
The N950's display requires two regulators.
Signed-off-by: Sebastian Reichel
---
drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 55 +++--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
b/drivers/gpu/drm/omapd
Hi Neil,
On 03-03-2017 09:07, Neil Armstrong wrote:
>
> The problem is that the HPD/RxSense is tied to this phy_mask and glued into
> the
> dw-hdmi driver.
>
> The *real* solution would be to completely separate the HPD/RxSense irq
> handling to
> a separate driver as a shared irq...
>
> If Jos
https://bugs.freedesktop.org/show_bug.cgi?id=100069
Kenneth Graunke changed:
What|Removed |Added
QA Contact|intel-3d-bugs@lists.freedes |dri-devel@lists.freedesktop
Hi Alexey,
On 03-03-2017 13:27, Alexey Brodkin wrote:
>
> So if I understood you correct here what I really need is just to get rid of
> existing check,
> right? I.e. the following is to be in v2 respin:
> --->8---
> diff --git a/drivers/gp
Hi Shashank,
On 03-03-2017 06:29, Shashank Sharma wrote:
> This patch does following:
> - Adds a new structure (drm_hdmi_info) in drm_display_info.
> This structure will be used to save and indicate if sink
> supports advanced HDMI 2.0 features
> - Adds another structure drm_scdc within drm_h
On 2017年03月03日 21:39, Tomeu Vizoso wrote:
Implement the .set_crc_source() callback and call the DP helpers
accordingly to start and stop CRC capture.
This is only done if this CRTC is currently using the eDP connector.
v3: Remove superfluous check on rockchip_crtc_state->output_type
v6: Remove
https://bugs.freedesktop.org/show_bug.cgi?id=100069
--- Comment #2 from Edward O'Callaghan ---
(In reply to Kenneth Graunke from comment #1)
> Assigning to the radeonsi driver until we know it's a general problem...
FYI Kenneth, I have access to a binary of this so could collect some data on
whe
https://bugs.freedesktop.org/show_bug.cgi?id=100068
Michel Dänzer changed:
What|Removed |Added
Attachment #130081|text/x-log |text/plain
mime type|
https://bugs.freedesktop.org/show_bug.cgi?id=100071
--- Comment #1 from Michel Dänzer ---
Can you either bisect LLVM, or create an apitrace which reproduces the problem?
--
You are receiving this mail because:
You are the assignee for the bug.___
dri-
https://bugs.freedesktop.org/show_bug.cgi?id=100058
--- Comment #3 from Michel Dänzer ---
(In reply to Adam Wolk from comment #0)
> I noticed my external display constantly turning on and off unless a DRI app
> is active (ie. running DRI_PRIME=1 glxgears).
Which GPU is the external display conne
The OF graph is not needed because the panel is a child of dsi. Add
the burst and esc clock frequency properties to the parent (DSI node).
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
di
The OF graph is not needed because the panel is a child of dsi. Remove
the ports node in DSI node, and port node in panel node.
Signed-off-by: Hoegeun Kwon
Reviewed-by: Andrzej Hajda
---
arch/arm/boot/dts/exynos3250-rinato.dts | 21 -
arch/arm/boot/dts/exynos4210-trats.dts
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