destep the problem.
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On 12/30/2016 2:18 AM, Daniel Vetter wrote:
> I just learned that &struct_name.member_name works and looks pretty
> even. It doesn't (yet) link to the member directly though, which would
> be really good for big structures or vfunc tables (where the
> per-member kerneldoc tends to be long).
>
> A
On 30 December 2016 at 12:12, David Herrmann wrote:
> Hi
>
> On Thu, Dec 29, 2016 at 9:48 PM, Daniel Vetter
> wrote:
>> - Remove the outdated hunk about driver documentation which somehow
>> got misplaced here in the split-up.
>>
>> - Collect all the testing&validation stuff together and give
On Sun, Jan 1, 2017 at 4:59 PM, Andrey Grodzovsky
wrote:
> This change allows usage of the new page_flip_target hook for
> drivers implementing the atomic path.
>
> Signed-off-by: Andrey Grodzovsky
> Reviewed-by: Harry Wentland
> Reviewed-by: Alex Deucher
Instead of patching your amdgpu versio
On Mon, Jan 02, 2017 at 11:53:03AM +0530, Archit Taneja wrote:
>
>
> On 12/30/2016 2:18 AM, Daniel Vetter wrote:
> > I just learned that &struct_name.member_name works and looks pretty
> > even. It doesn't (yet) link to the member directly though, which would
> > be really good for big structures
On Sat, Dec 31, 2016 at 07:48:38AM +0530, vathsala nagaraju wrote:
> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encodin
On Sat, 31 Dec 2016, vathsala nagaraju wrote:
> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
> Form
In case of HW trigger mode, sysreg register should be configured to
enable TE functionality. The patch refactors also trigger setup function.
Signed-off-by: Andrzej Hajda
---
v2: fixed bitop operator (thanks Ilia)
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 40 +--
The drm_mode_config helper private field points to a structure of
function pointers that don't need to be modified at runtime. Make it
const.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/arm/malidp_drv.c | 2 +-
drivers/gpu/drm/drm_atomic_helper.c| 2 +-
drivers/gpu/drm/
Hi Randy,
Thanks for the patch.
On Mon, Jan 02, 2017 at 04:50:04PM +0800, Randy Li wrote:
> The formats added by this patch are:
> V4L2_PIX_FMT_P010
> V4L2_PIX_FMT_P010M
> Currently, none of driver uses those format, but some video device
> has been confirmed with could as those forma
On Sun, Jan 01, 2017 at 03:16:31PM -0600, vcaputo at pengaru.com wrote:
> Hi Chris,
>
> I've uncovered a bug in i915_gem_request_alloc():
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/i915/i915_gem_request.c?h=v4.9#n425
>
> ctx here may be NULL, and i915_g
Am 15.12.2016 um 23:43 schrieb Grazvydas Ignotas:
> On Thu, Dec 15, 2016 at 4:12 PM, Christian König
> wrote:
>> Regarding which error code to return I think that Emil has the right idea
>> here.
>>
>> Returning -EINVAL usually means that userspace provided an invalid value,
>> but in this case i
Hi,
On Mon, Jan 02, 2017 at 06:53:16PM +0800, ayaka wrote:
>
>
> On 01/02/2017 05:10 PM, Sakari Ailus wrote:
> >Hi Randy,
> >
> >Thanks for the patch.
> >
> >On Mon, Jan 02, 2017 at 04:50:04PM +0800, Randy Li wrote:
> >>The formats added by this patch are:
> >>V4L2_PIX_FMT_P010
> >>V4L2_
On 30.12.2016 07:58, Hoegeun Kwon wrote:
> Purpose of this patch is add support for S6E3HA2 AMOLED panel on
> the TM2 board. The first patch adds support for S6E3HA2 panel
> device tree document and driver, the second patch add support for
> S6E3HA2 panel device tree.
>
> Changes for V3:
>
> - In t
Hi Daniel,
Thank you for the patch.
On Wednesday 08 Jun 2016 17:15:36 Daniel Vetter wrote:
> To facilitate easier reviewing this is split out from the overall
> nonblocking commit rework. It just rolls out the helper functions
> and uses them in the main drm_atomic_helper_commit() function
> to m
Hi
On Mon, Jan 2, 2017 at 11:41 AM, Rainer Hochecker
wrote:
> From: Rainer Hochecker
>
> Add fourcc codes for 16bit planes. Required by mesa for
> eglCreateImageKHR to access P010 surfaces created by vaapi.
>
> Signed-off-by: Rainer Hochecker
> ---
> include/uapi/drm/drm_fourcc.h | 6 ++
>
Hi Daniel,
On Wednesday 08 Jun 2016 14:18:58 Daniel Vetter wrote:
> atomic_flush seems to be the right place, right after we commit the
> plane updates. Again use the fullproof version, since the pipe might
> be off.
>
> Cc: Boris Brezillon
> Cc: Maxime Ripard
> Signed-off-by: Daniel Vetter
>
for the bug.
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Hi,
here are the patches that remain to be merged in this series.
Since v13, I have added a patch that makes open() block until the first
CRC comes. This is because otherwise, userspace would need to guess how
much time this particular HW takes to become ready to generate frame
CRCs. This patch c
There's no reason any more for callers of this function to take the lock
themselves, so just move the lock to the function to avoid confusion and
bugs when more callers are contributed.
Signed-off-by: Tomeu Vizoso
Reviewed-by: Emil Velikov
Reviewed-by: Robert Foss
---
drivers/gpu/drm/drm_debu
Don't return from the open() call on the crc/data file until the HW has
produced a first frame, as there's great variability in when the HW is
able to do that and userspace shouldn't have to guess when this specific
HW is ready to start giving frame CRCs.
Signed-off-by: Tomeu Vizoso
---
drivers
The core provides now an ABI to userspace for generation of frame CRCs,
so implement the ->set_crc_source() callback and reuse as much code as
possible with the previous ABI implementation.
When handling the pageflip interrupt, we skip 1 or 2 frames depending on
the HW because they contain wrong v
Use drm_accurate_vblank_count so we have the full 32 bit to represent
the frame counter and userspace has a simpler way of knowing when the
counter wraps around.
Signed-off-by: Tomeu Vizoso
Reviewed-by: Emil Velikov
Reviewed-by: Robert Foss
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
1 fi
On Wed, 28 Dec 2016, Daniel Vetter wrote:
> On Wed, Dec 28, 2016 at 01:06:26PM +0200, Jani Nikula wrote:
>> No reason not to be const.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Daniel Vetter
Pushed, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/drm_edid.c | 6 +++---
>
ause the code to error out early. Technically we wouldn't be able to
ever extend one type of bus or device info, though.
Thierry
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Cbrcm,bcm2835-vc4
I think the full name is appropriate for bus info because it's about the
closest thing we have to address the device (the equivalent to domain,
bus, device and function numbers).
The list of compatible strings might be suitable for device information
and might be usefu
On Mon, Jan 02, 2017 at 01:23:23PM +0100, David Herrmann wrote:
> Hi
>
> On Mon, Jan 2, 2017 at 11:41 AM, Rainer Hochecker
> wrote:
> > From: Rainer Hochecker
> >
> > Add fourcc codes for 16bit planes. Required by mesa for
> > eglCreateImageKHR to access P010 surfaces created by vaapi.
> >
> >
From: Hans Verkuil
This patch series adds the hotplug detect notifier code, based on Russell's
code:
https://patchwork.kernel.org/patch/9277043/
It adds support for it to the exynos_hdmi drm driver, adds support for
it to the CEC framework and finally adds support to the s5p-cec driver,
which
From: Hans Verkuil
Add support for video hotplug detect and EDID/ELD notifiers, which is used
to convey information from video drivers to their CEC and audio counterparts.
Based on an earlier version from Russell King:
https://patchwork.kernel.org/patch/9277043/
The hpd_notifier is a reference
From: Hans Verkuil
Implement the HPD notifier support to allow CEC drivers to
be informed when there is a new EDID and when a connect or
disconnect happens.
Signed-off-by: Hans Verkuil
Tested-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/Kconfig | 1 +
drivers/gpu/drm/exynos/exynos_h
From: Hans Verkuil
Support the HPD notifier framework, simplifying drivers that
depend on this.
Signed-off-by: Hans Verkuil
Tested-by: Marek Szyprowski
---
drivers/media/cec/cec-core.c | 50
include/media/cec.h | 15 +
2 files
From: Hans Verkuil
By using the HPD notifier framework there is no longer any reason
to manually set the physical address. This was the one blocking
issue that prevented this driver from going out of staging, so do
this move as well.
Update the bindings documenting the new hdmi phandle and
updat
Here's a v2 with the part of the series that didn't get pushed yet.
Patch 2 has the suggestions from Daniel applied.
Thanks,
Gabriel Krisman Bertazi (2):
exynos_drm: Clean up duplicated assignment in exynos_drm_driver
drm: Document deprecated load/unload hook
drivers/gpu/drm/exynos/exynos_d
num_ioctls is already assigned when declaring the exynos_drm_driver
structure. No need to duplicate it here.
Signed-off-by: Gabriel Krisman Bertazi
CC: Inki Dae
CC: Joonyoung Shim
CC: Seung-Woo Kim
CC: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
1 file changed, 1 deleti
v2:
- Replace discouraged with deprecated
- Link to new initialization/teardown functions
Signed-off-by: Gabriel Krisman Bertazi
---
include/drm/drm_drv.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
inde
On Sat, Dec 31, 2016 at 2:55 AM, James Cloos wrote:
>> "AD" == Alex Deucher writes:
>
> AD> That option is just a carry over from when the amdgpu was copied from
> AD> radeon. There is some code for older asics left over from when the
> AD> code was originally ported from radeon. If you wan
:
<https://lists.freedesktop.org/archives/dri-devel/attachments/20170102/93f8fbd5/attachment.html>
> "AD" == Alex Deucher writes:
AD> The GPU firmware is not involved in display or audio at all.
Oh. Thanks for that!
In that case the bug showed up some time between 3.19.0 and 4.1.0.
git tag tells me 3.19 was the last 3.
Only 14.56+ bits worth of commits between those two tags. ;)
-Jim
Signed-off-by: Gabriel Krisman Bertazi
---
drivers/gpu/drm/drm_cache.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index a7916e5f8864..b52e16e2b8ef 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu
Continue to clean up drmP.h by moving the cache flushing functions into
it's own header file.
Signed-off-by: Gabriel Krisman Bertazi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/vgem/vgem_drv.h | 1 +
include/drm/drmP.h | 5 -
include/drm/drm_cache.h | 4 ++
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Laurent Pinchart writes:
> The drm_mode_config helper private field points to a structure of
> function pointers that don't need to be modified at runtime. Make it
> const.
Reviewed-by: Gabriel Krisman Bertazi
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helps.
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t; the hang.
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On Tue, 3 Jan 2017 10:59:29 +0800
Zhenyu Wang wrote:
> On 2017.01.03 10:42:39 +1100, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the drm-intel-fixes tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'in
This series enables psr2 on idle on screen for y cordinate panel.
Code is tested on sharp 32X18 edp 1.4 y cordinate enabled panel.
if system enters psr2, the system must go to deep sleep state.
Can be verifed by checking psr2_status register bit 31:28.
DEEP_SLEEP[value 8] must be entered while in
Hi,
On 12/26/2016 09:23 PM, H. Nikolaus Schaller wrote:
> Signed-off-by: H. Nikolaus Schaller
I did compile and boot tests after each patch when doing the conversion,
but this certainly skipped because these were 'hidden' by
#ifdef PRINT_VERBOSE_VM_TIMINGS
which is not a Kconfig option and need
Screen freeze observed if AUX_FRAME_SYNC is not disabled
on psr2 exit.AUX_FRAME_SYNC needed for psr2 is enabled during
psr2 entry. It must be disabled on psr2 exit.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/intel_psr.c
Hi Daniel,
Thank you for the patch.
On Friday 19 Aug 2016 22:50:38 Daniel Vetter wrote:
> Everyone knows them, except all the new folks joining from the ARM
> side haven't lived through all the pain of the past years and are
> entirely surprised when I raise this. Definitely time to document
> th
PSR2 vsc revision number hb2( as per table 6-11)is updated to
4 or 5 based on Y cordinate and Colorimetry Format as below
04h = 3D stereo + PSR/PSR2 + Y-coordinate.
05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
Format indication. A DP Source device is allowed to indicate
Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.
Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.
v2: (Jani)
- Initialize variables to 0
-
The formats added by this patch are:
V4L2_PIX_FMT_P010
V4L2_PIX_FMT_P010M
Currently, none of driver uses those format, but some video device
has been confirmed with could as those format for video output.
The Rockchip's new decoder has supported those format for profile_10
HEVC/AVC
On Wednesday 14 December 2016 03:24 PM, Tomi Valkeinen wrote:
> On 13/12/16 12:09, Bartosz Golaszewski wrote:
>> Add the vga-bridge node to the board DT together with corresponding
>> ports and vga connector. This allows to retrieve the edid info from
>> the display automatically.
>>
>> Signed-off-
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: vathsala nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
dri
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format. Rockchip's vop support this
video format(little endian only) as the input video format.
Signed-off-by: Randy Li
---
include/uapi/drm/drm_fourcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/ua
As per edp1.4 spec , alpm is required for psr2 operation as it's
used for all psr2 main link power down management and alpm enable
bit must be set for psr2 operation.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: vathsala nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/i915_drv
On 01/02/2017 05:10 PM, Sakari Ailus wrote:
> Hi Randy,
>
> Thanks for the patch.
>
> On Mon, Jan 02, 2017 at 04:50:04PM +0800, Randy Li wrote:
>> The formats added by this patch are:
>> V4L2_PIX_FMT_P010
>> V4L2_PIX_FMT_P010M
>> Currently, none of driver uses those format, but some vid
Reports live state of PSR2 form PSR2_STATUS register.
bit field 31:28 gives the live state of PSR2.
It can be used to check if system is in deep sleep,
selective update or selective update standby.
During video play back, we can use this to check
if system is entering SU mode or not.
when system i
On Mon, Jan 02, 2017 at 03:19:07PM +0100, Hans Verkuil wrote:
> From: Hans Verkuil
>
> By using the HPD notifier framework there is no longer any reason
> to manually set the physical address. This was the one blocking
> issue that prevented this driver from going out of staging, so do
> this mov
On Sun, Jan 1, 2017 at 11:40 PM, Laurent Pinchart
wrote:
> Hi Daniel,
>
> Thank you for the patch.
>
> On Friday 19 Aug 2016 22:50:38 Daniel Vetter wrote:
>> Everyone knows them, except all the new folks joining from the ARM
>> side haven't lived through all the pain of the past years and are
>> e
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_S
Psr2 is enabled only for y cordinate panels.Once GTC (global time code)
is implemented,this restriction is removed so that psr2
can work on panels without y cordinate support.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/
Those pixel formats comes from Gstreamer and ffmpeg. Currently,
the VOP(video output mixer) found on RK3288 and future support
those pixel formats are input. Also the decoder on RK3288
could use them as output.
Randy Li (2):
drm_fourcc: Add new P010 video format
[media] v4l: Add 10-bits per ch
PSR1 and PSR2 enable sequence are mutually exclusive.
Register SRD_PERF_COUNT increments while system is in psr1.
This register is not valid for psr2.while in psr2,SRD_PERF_COUNT
is always 0.
Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case.
Also, if dc6 is disabled via kernel
Hi Archit,
On Wednesday 14 December 2016 10:35 AM, Archit Taneja wrote:
>
>
> On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
>> THS8135 is a configurable video DAC, but no configuration is actually
>> necessary to make it work.
>>
>> For now use the dumb-vga-dac driver to support it.
>
> Qu
On Wednesday 14 December 2016 03:27 PM, Tomi Valkeinen wrote:
> On 13/12/16 12:09, Bartosz Golaszewski wrote:
>> The tilcdc node name is 'display' as per the ePAPR 1.1 recommendation.
>> The label is also 'display', but change it to 'lcdc' to make it clear
>> what the underlying hardware is.
>>
>>
HDMI 2.0 introduces a new sampling mode called YCbCr 4:2:0.
According to the spec the EDID may contain two blocks that
signal this sampling mode:
- YCbCr 4:2:0 Video Data Block
- YCbCr 4:2:0 Video Capability Map Data Block
The video data block contains the list of vic's were
only Y
On Tuesday 13 December 2016 03:39 PM, Bartosz Golaszewski wrote:
> At maximum CPU frequency of 300 MHz the maximum pixel clock frequency
> is 37.5 MHz[1]. We must filter out any mode for which the calculated
> pixel clock rate would exceed this value.
>
> Specify the max-pixelclock property for th
Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.
Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.
Cc: Rodrigo Vivi
Cc: Jim Bride
S
full GR1616 in there. Althogh GR32 could work
> too I suppose.
>
> And what about RG16?
>
> >
> > Also, please put dri-devel on CC.
> >
> > Thanks
> > David
> >
> > > /* 8 bpp RGB */
> > > #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /*
> [7:0] R:G:B 3:3:2 */
> > > #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /*
> [7:0] B:G:R 2:3:3 */
> > > --
> > > 2.9.3
> > >
> > ___
> > dri-devel mailing list
> > dri-devel at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Ville Syrjälä
> Intel OTC
>
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On 01 January, 2017 21:24 CET, Peter Senna Tschudin wrote:
[ ... ]
> +static void ge_b850v3_lvds_dp_detach(struct drm_bridge *bridge)
> +{
> + struct ge_b850v3_lvds_dp *ptn_bridge
> + = bridge_to_ge_b850v3_lvds_dp(bridge);
> + struct i2c_client *ge_b850v3_lvds_dp_i
Althogh GR32 could work
> too I suppose.
>
> And what about RG16?
>
> >
> > Also, please put dri-devel on CC.
> >
> > Thanks
> > David
> >
> > > /* 8 bpp RGB */
> > > #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /*
> [7:0] R:G:B 3:3:2 */
> > > #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /*
> [7:0] B:G:R 2:3:3 */
> > > --
> > > 2.9.3
> > >
> > ___
> > dri-devel mailing list
> > dri-devel at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Ville Syrjälä
> Intel OTC
>
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On Fri, Dec 30, 2016 at 05:33:38PM +0100, Daniel Vetter wrote:
> I reported the include issue for tracepoints a while ago, but nothing
> seems to have happened. Now it bit us, since the drm_mm_print
> conversion was broken for armada. Fix them both.
Nothing's happened because I haven't had an oppo
On 01/02/2017 07:07 PM, Sakari Ailus wrote:
> Hi,
>
> On Mon, Jan 02, 2017 at 06:53:16PM +0800, ayaka wrote:
>>
>> On 01/02/2017 05:10 PM, Sakari Ailus wrote:
>>> Hi Randy,
>>>
>>> Thanks for the patch.
>>>
>>> On Mon, Jan 02, 2017 at 04:50:04PM +0800, Randy Li wrote:
The formats added by th
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