Hi,
On 11/25/2016 12:07 AM, Fabio Estevam wrote:
> Hi Laurent,
>
> On Thu, Nov 24, 2016 at 7:16 PM, Laurent Pinchart
> wrote:
>> Hi Andy,
>>
>> As the author of the DW-HDMI DT bindings this question is addressed to you,
>> but information from anyone is more than welcome.
>>
>> The DT bindings sp
Hello Fabio and Vladimir,
Thank you for your quick responses.
On Friday 25 Nov 2016 00:16:00 Vladimir Zapolskiy wrote:
> On 11/25/2016 12:07 AM, Fabio Estevam wrote:
> > On Thu, Nov 24, 2016 at 7:16 PM, Laurent Pinchart wrote:
> >> Hi Andy,
> >>
> >> As the author of the DW-HDMI DT bindings this
>No critial patch but it make sure to unmap the region
>if HDMI probing failed, and it includes two trivial fixups.
>
I've cherry-picked the hdmi fix, but I think the other two patches
should go in -next
at this stage,
Thanks,
Dave.
Hi Daniel,
On Wednesday 23 Nov 2016 08:55:37 Daniel Vetter wrote:
> On Tue, Nov 22, 2016 at 08:23:38PM +0200, Laurent Pinchart wrote:
> > On Tuesday 22 Nov 2016 10:07:53 John Stultz wrote:
> >> On Tue, Nov 22, 2016 at 9:38 AM, John Stultz wrote:
> >>> Interestingly, without the msleep added in thi
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from Vedran MiletiÄ ---
Still broken with llvm r287905287905.
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al, Portal 2, and Dota 2.
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Hi Linus,
Seems to be quietening down nicely, a few mediatek, one exynos and one
hdlcd fix,
along with 2 amd fixes.
Dave.
The following changes since commit 9c763584b7c8911106bb77af7e648bef09af9d80:
Linux 4.9-rc6 (2016-11-20 13:52:19 -0800)
are available in the git repository at:
git://pe
On Fri, Nov 25, 2016 at 1:23 AM, Laurent Pinchart
wrote:
>> > Daniel, why do we have an API the is clearly related to interrupt handling
>> > but requires the caller to implement a workqueue ?
>>
>> Because in general you need that workqueue anyway, and up to now there was
>> no driver ever who di
On Thu, Nov 24, 2016 at 10:32:59PM +0200, Jyri Sarha wrote:
> On 11/24/16 14:56, Tomi Valkeinen wrote:
> > On 24/11/16 14:03, Jyri Sarha wrote:
> >
> >>> The suspend/resume you're talking there is the system suspend/resume.
> >>> That's quite different than the runtime suspend/resume, and they sho
On Thu, Nov 24, 2016 at 02:35:45PM +0300, Dan Carpenter wrote:
> The drm_dev_alloc() function returns error pointers. It never returns
> NULLs.
>
> Fixes: 5e0df3a08f3d ("drm/hisilicon/hibmc: Add hisilicon hibmc drm master
> driver")
> Signed-off-by: Dan Carpenter
Applied to drm-misc, thanks.
-
On Thu, Nov 24, 2016 at 05:30:26PM +0100, Arnd Bergmann wrote:
> When CONFIG_PM_SLEEP is disabled, we get a harmless warning
>
> drm/hisilicon/hibmc/hibmc_drm_drv.c:115:12: error: âhibmc_pm_resumeâ
> defined but not used [-Werror=unused-function]
> drm/hisilicon/hibmc/hibmc_drm_drv.c:97:12: e
a graphical environment. How can I
help to completely fix the issue with this card?
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Changes since v4:
- "drm/bridge: Add ti-tfp410 DVI transmitter driver"
- Put i2c behind #if IS_ENABLED(CONFIG_I2C)
- "drm/tilcdc: Add drm bridge support for attaching drm bridge drivers"
- Use exsisting infrastructure to hookup crtc mode validation code
to newly connected connector, whether
Add very basic ti-tfp410 DVI transmitter driver. The only feature
separating this from a completely dummy bridge is the EDID read
support trough DDC I2C. Even that functionality should be in a
separate generic connector driver. However, because of missing DRM
infrastructure support the connector is
Recover from sync lost error flood by resetting the LCDC instead of
turning off the SYNC_LOST error IRQ. When LCDC starves on limited
memory bandwidth it may sometimes result an error situation when the
picture may have shifted couple of pixels to right and SYNC_LOST
interrupt is generated on every
Adds drm bride support for attaching drm bridge drivers to tilcdc. The
decision whether a video port leads to an external encoder or bridge
is made simply based on remote device's compatible string. The code
has been tested with BeagleBone-Black with and without BeagleBone
DVI-D Cape Rev A3 using t
Move "ti,tfp410.txt" from display/ti to display/bridge before adding
generic (non omapdrm/dss specific) implementation and new features.
Signed-off-by: Jyri Sarha
---
Documentation/devicetree/bindings/display/{ti => bridge}/ti,tfp410.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rena
The git branch bellow is updated.
Changes since v3:
- "drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC"
- disable sync-lost irq also for rev1 LCDC
- LCDC_V1_SYNC_LOST_ENA to LCDC_V1_SYNC_LOST_INT_ENA
- "drm/tilcdc: Enable palette loading for revision 2 LCDC too"
- dis
From: Bartosz Golaszewski
Revision 1 of the IP doesn't work if we don't load the palette (even
if it's not used, which is the case for the RGB565 format).
Add a function called from tilcdc_crtc_enable() which performs all
required actions if we're dealing with a rev1 chip.
Signed-off-by: Bartos
Revision 1 LCDC support also sync lost errors and can benefit from
sync lost recovery routine.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 35 ---
drivers/gpu/drm/tilcdc/tilcdc_regs.h | 1 +
2 files changed, 21 insertions(+), 15 deletions
Load palette at the end of mode_set_nofb(). Moving the palette loading
to mode_set_nofb() saves us from storing and restoring of framebuffer
addresses in dma registers that were just recently written there.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 25 +
Set LCDC_PALETTE_LOAD_MODE bit-field with new tilcdc_write_mask()
instead of tilcdc_set(). Setting a bit-fields with tilcdc_set() is
fundamentally broken.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/dri
Configure video mode to HW in enable() call back. There is no reason
to do it before that. This makes PM functions way easier because there
is no HW context to save when screen is for instance blanked. This
patch removes mode_set_nofb() call back from tilcdc.
Signed-off-by: Jyri Sarha
---
driver
Add tilcdc_write_mask() for handling register field wider than one bit
and mask values for those fields.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_regs.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h
b/drivers/gpu/drm/t
Failed tilcdc_crtc_create() error handling was broken, this patch
should fix it.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 +++-
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 11 ---
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 +-
3 files changed, 12 insertio
We should wait for the last frame to complete before shutting things
down also on LCDC rev 1.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 18 +++---
drivers/gpu/drm/tilcdc/tilcdc_regs.h | 1 +
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/d
Add timeout wait for palette loadind to complete. We do not want to
hang forever if palette loaded interrupt does not arrive for some
reason.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
The LCDC revision 2 documentation also mentions the mandatory palette
for true color modes. Even if the rev 2 LCDC appears to work just fine
without the palette being loaded loading it helps in testing the
feature.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 90 +
Add the dumb-vga-dac node to the board DT together with corresponding
ports and vga connector. This allows to retrieve the edid info from
the display automatically.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/boot/dts/da850-lcdk.dts | 58
arch/arm/boo
This enables the dumb-vga-dac driver by default for davinci boards.
The driver is needed for tilcdc support on da850-lcdk board.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/configs/davinci_all_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/davinci_all_defco
bug.
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Hi Laurent,
Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart:
> Hi Andy,
>
> As the author of the DW-HDMI DT bindings this question is addressed to you,
> but information from anyone is more than welcome.
>
> The DT bindings specify two clocks named "iahb" and "isfr" but don'
On Fri, 25 Nov 2016 17:41:51 +0800
Icenowy Zheng wrote:
> After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation.
The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not
use the legacy u-boot, I don't know which can be the rate of the DE.
> However, it cannot r
This is MT2701 DRM support PATCH v10, based on 4.9-rc1.
We add DSI interrupt control, transfer function for MIPI DSI panel support.
Most codes are the same, except some register changed.
For example:
- DISP_OVL address offset changed, color format definition changed.
- DISP_RDMA fifo size change
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl'
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma'
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 +--
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +--
2 file
There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
MIPI_TX pll setting changed.
And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.
Signed-off-by: YT She
We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 76 -
drivers/gpu/drm/mediatek/mtk_drm_ddp.
Add BLS component for PWM + GAMMA function
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 -
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gp
update connections for OVL, RDMA, BLS, DSI
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index b77d456..a9b209c 1006
cleaning up unused define and refine function name and variable
Signed-off-by: shaoming chen
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 77 --
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 8 ++--
2 files changed, 41 insertions(+), 44 deletio
From: shaoming chen
add dsi interrupt control
Signed-off-by: shaoming chen
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 4efeb38..
From: shaoming chen
add dsi read/write commands for transfer function
Signed-off-by: shaoming chen
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 168 -
1 file changed, 166 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/g
modify data rate limitation (>lGbps/lane) for mipitx
Signed-off-by: shaoming chen
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mipi_
modify dsi enter ultra low power mode method
Signed-off-by: shaoming chen
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index d03a0f1.
add non-continuous clock mode and EOT packet control for dsi
Signed-off-by: shaoming chen
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 01df829..
This patch update enable/disable flow of DSI module.
Original flow works on there is a bridge chip: DSI -> bridge -> panel.
In this case: DSI -> panel, the DSI sub driver flow should be updated.
We need to initialize DSI first so that we can send commands to panel.
Signed-off-by: shaoming chen
Si
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 6 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 17 +
https://bugzilla.kernel.org/show_bug.cgi?id=188621
Bug ID: 188621
Summary: Function kfd_wait_on_events() does not set error code
when the call to copy_from_user() fails
Product: Drivers
Version: 2.5
Kernel Version: linux-4.9-rc6
https://bugzilla.kernel.org/show_bug.cgi?id=188631
Bug ID: 188631
Summary: Function vc4_cl_lookup_bos() does not set error code
when the call to drm_malloc_ab() fails
Product: Drivers
Version: 2.5
Kernel Version: linux-4.9-rc6
https://bugzilla.kernel.org/show_bug.cgi?id=188911
Bug ID: 188911
Summary: Function qxl_release_alloc() returns an improper value
when the call to kmalloc() fails, resulting in bad
memory access
Product: Drivers
V
lt;https://lists.freedesktop.org/archives/dri-devel/attachments/20161125/258169b4/attachment.html>
2016-11-25 10:02 GMT+01:00 Jyri Sarha :
> Changes since v4:
> - "drm/bridge: Add ti-tfp410 DVI transmitter driver"
> - Put i2c behind #if IS_ENABLED(CONFIG_I2C)
> - "drm/tilcdc: Add drm bridge support for attaching drm bridge drivers"
> - Use exsisting infrastructure to hookup crtc mode validat
2016-11-25 10:09 GMT+01:00 Jyri Sarha :
> The git branch bellow is updated.
>
> Changes since v3:
> - "drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC"
> - disable sync-lost irq also for rev1 LCDC
> - LCDC_V1_SYNC_LOST_ENA to LCDC_V1_SYNC_LOST_INT_ENA
> - "drm/tilcdc: En
https://bugzilla.kernel.org/show_bug.cgi?id=188621
--- Comment #1 from Oded Gabbay ---
I'll look into it.
Thanks for the bug.
Oded
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Hi Vladimir,
On Thu, Nov 24, 2016 at 8:16 PM, Vladimir Zapolskiy
wrote:
> By the way while we're discussing DW HDMI bindings specific to iMX,
> I would recommend to remove utterly hackish and iMX only "gpr"
> property from the example in bindings/display/bridge/dw_hdmi.txt
What if we get rid of
Silences
./include/drm/drm_drv.h:295: warning: Incorrect use of kernel-doc format
Signed-off-by: Chris Wilson
---
include/drm/drm_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index aad8bbacd1f0..52bf44e2b5cc 100644
--- a/include/drm/d
Hi Laurent,
On Thu, Nov 24, 2016 at 9:26 PM, Laurent Pinchart
wrote:
> Another question I have about the bus clock (CC'ing the devicetree mailing
> list as well as the clock maintainers) is whether it should be made optional.
> The clock is obviously mandatory from a hardware point of view (give
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Hi Fabio,
On 11/25/2016 02:29 PM, Fabio Estevam wrote:
> Hi Vladimir,
>
> On Thu, Nov 24, 2016 at 8:16 PM, Vladimir Zapolskiy
> wrote:
>
>> By the way while we're discussing DW HDMI bindings specific to iMX,
>> I would recommend to remove utterly hackish and iMX only "gpr"
>> property from the ex
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Hi Vladimir,
On Fri, Nov 25, 2016 at 11:00 AM, Vladimir Zapolskiy
wrote:
> according to the DTSI files in the vanilla kernel DW HDMI IP is found
> only on iMX6Q/D and iMX6DL/iMX6S SoCs (but please double check it),
> so this approach should work ideally.
After thinking more about this I think w
Am 24.11.2016 um 18:55 schrieb Logan Gunthorpe:
> Hey,
>
> On 24/11/16 02:45 AM, Christian König wrote:
>> E.g. it can happen that PCI device A exports it's BAR using ZONE_DEVICE.
>> Not PCI device B (a SATA device) can directly read/write to it because
>> it is on the same bus segment, but PCI de
Am 24.11.2016 um 17:42 schrieb Jason Gunthorpe:
> On Wed, Nov 23, 2016 at 06:25:21PM -0700, Logan Gunthorpe wrote:
>>
>> On 23/11/16 02:55 PM, Jason Gunthorpe wrote:
> Only ODP hardware allows changing the DMA address on the fly, and it
> works at the page table level. We do not need specia
Hi Fabio,
On Friday 25 Nov 2016 10:43:04 Fabio Estevam wrote:
> On Thu, Nov 24, 2016 at 9:26 PM, Laurent Pinchart wrote:
> > Another question I have about the bus clock (CC'ing the devicetree mailing
> > list as well as the clock maintainers) is whether it should be made
> > optional. The clock is
.0, didn't try 3.8.x.
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On 11/25/2016 03:06 PM, Fabio Estevam wrote:
> Hi Vladimir,
>
> On Fri, Nov 25, 2016 at 11:00 AM, Vladimir Zapolskiy
> wrote:
>
>> according to the DTSI files in the vanilla kernel DW HDMI IP is found
>> only on iMX6Q/D and iMX6DL/iMX6S SoCs (but please double check it),
>> so this approach should
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On Fri, Nov 25, 2016 at 12:34:27PM +, Chris Wilson wrote:
> Silences
>
> ./include/drm/drm_drv.h:295: warning: Incorrect use of kernel-doc format
>
> Signed-off-by: Chris Wilson
Applied to drm-misc, thanks.
-Daniel
> ---
> include/drm/drm_drv.h | 2 ++
> 1 file changed, 2 insertions(+)
>
25.11.2016, 18:22, "Jean-Francois Moine" :
> On Fri, 25 Nov 2016 17:41:51 +0800
> Icenowy Zheng wrote:
>
>> Â After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation.
>
> The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not
> use the legacy u-boot, I don't kno
On Fri, 25 Nov 2016 13:27:20 +0800
Icenowy Zheng wrote:
> > + assigned-clocks = <&ccu CLK_PLL_DE>,
>
> Cannot get the patch built on 4.9-rc, as CLK_PLL_DE is not an exported clock.
Hi,
Sorry, I forgot it. The symbol goes to
include/dt-bindings/clock/sun8i-h3-ccu.h
as:
#define CLK_PLL_DE
Hi:
On 2016å¹´11æ25æ¥ 07:26, Laurent Pinchart wrote:
> Hello Fabio and Vladimir,
>
> Thank you for your quick responses.
>
> On Friday 25 Nov 2016 00:16:00 Vladimir Zapolskiy wrote:
>> On 11/25/2016 12:07 AM, Fabio Estevam wrote:
>>> On Thu, Nov 24, 2016 at 7:16 PM, Laurent Pinchart wrote:
>>>
20.11.2016, 20:07, "Jean-Francois Moine" :
> Signed-off-by: Jean-Francois Moine
> ---
> Â arch/arm/boot/dts/sun8i-h3.dtsi | 51
> +
> Â 1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> in
20.11.2016, 20:12, "Jean-Francois Moine" :
> Signed-off-by: Jean-Francois Moine
> ---
> Â arch/arm/boot/dts/sun8i-h3.dtsi | 51
> +
> Â 1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> in
Hi Andy,
On Friday 25 Nov 2016 10:56:53 Andy Yan wrote:
> On 2016å¹´11æ25æ¥ 07:26, Laurent Pinchart wrote:
> > On Friday 25 Nov 2016 00:16:00 Vladimir Zapolskiy wrote:
> >> On 11/25/2016 12:07 AM, Fabio Estevam wrote:
> >>> On Thu, Nov 24, 2016 at 7:16 PM, Laurent Pinchart wrote:
> Hi Andy
On Fri, Nov 25, 2016 at 1:22 PM, Laurent Pinchart
wrote:
>> I got the clock name from I.MX6Q TRM, I also checked the name again
>> with Rockchip IC design team now, hope to get some new information soon.
>
> Thank you. While at it, could you ask them which version of the DW HDMI IP
> used in the
We are told not to set plane_state->fb directly, but use
drm_atomic_set_fb_for_plane() instead. Using the helper, means one less
piece of code that needs fixing should the interface change...
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 6 +-
1 file changed, 1 inser
We can simplify the code greatly if both legacy and atomic paths updated
the references as they assigned the framebuffer to the planes. Long
before framebuffer reference counting was added, the code had to keep
the old_fb around until after the operation was completed - but now we
can simply leave
In a couple of places currently, and with the intent to add more, we
update a pointer to a framebuffer to hold a new fb reference (evicting
the old).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_atomic.c | 8 ++--
include/drm/drm_framebuffer.h | 18 ++
2 files change
It has been determined that the maximum resolution supported correctly
by tilcdc rev1 on da850 SoCs is 800x600 at 60. Due to memory throughput
constraints we must filter out higher modes.
Specify the max-bandwidth property for the display node for
da850-based boards.
Signed-off-by: Bartosz Golasz
Hi Philipp,
On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote:
> Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart:
> > Hi Andy,
> >
> > As the author of the DW-HDMI DT bindings this question is addressed to
> > you, but information from anyone is more than welcome.
> >
> > Th
Hi Fabio,
On Friday 25 Nov 2016 13:29:37 Fabio Estevam wrote:
> On Fri, Nov 25, 2016 at 1:22 PM, Laurent Pinchart wrote:
> >> I got the clock name from I.MX6Q TRM, I also checked the name again
> >> with Rockchip IC design team now, hope to get some new information soon.
> >
> > Thank you. While
Hi Dave,
Thanks for pulling the previous patch for HDLCD. Unfortunately,
yesterday Robin Murphy discovered another issue while playing with
CMA allocation sizes, which he has submitted a fix for. If you
think it is too late for this to go into v4.9, please let me know.
Many thanks,
Liviu
The fol
I previously sent these patches separately, but since they're touching
the same files while coming from different trees, I decided to post
it again in a series to make applying them easier.
Bartosz Golaszewski (3):
ARM: da850-lcdk: add the dumb-vga-dac node
ARM: dts: da850: specify the maximum
It has been determined that the maximum resolution supported correctly
by tilcdc rev1 on da850 SoCs is 800x600 at 60. Due to memory throughput
constraints we must filter out higher modes.
Specify the max-bandwidth property for the display node for
da850-based boards.
Signed-off-by: Bartosz Golasz
Add the dumb-vga-dac node to the board DT together with corresponding
ports and vga connector. This allows to retrieve the edid info from
the display automatically.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/boot/dts/da850-lcdk.dts | 58
arch/arm/boo
Currently the memory controller and master priorities drivers are
enabled in da850.dtsi. For boards for which there are no settings
defined, this makes these drivers emit error messages.
Disable the nodes in da850.dtsi and only enable them for da850-lcdk -
the only board that currently needs them.
Am Freitag, den 25.11.2016, 17:45 +0200 schrieb Laurent Pinchart:
> Hi Philipp,
>
> On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote:
> > Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart:
> > > Hi Andy,
> > >
> > > As the author of the DW-HDMI DT bindings this question is add
Hi,
This is v3 of my series introducing a new connector type:
DRM_MODE_CONNECTOR_WRITEBACK
See v1 and v2 here: [1] [2]
Writeback connectors are used to expose the memory writeback engines
found in some display controllers, which can write a CRTC's
composition result to a memory buffer.
This is u
We're going to use the same format list for output formats, so rename
everything related to input formats to avoid confusion.
Signed-off-by: Brian Starkey
Reviewed-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_hw.c | 24
drivers/gpu/drm/arm/malidp_hw.h |8
Add a layer bit for the SE memory-write, and add it to the pixel format
matrix for DP550/DP650.
Signed-off-by: Brian Starkey
---
drivers/gpu/drm/arm/malidp_hw.c | 28 ++--
drivers/gpu/drm/arm/malidp_hw.h |1 +
2 files changed, 15 insertions(+), 14 deletions(-)
diff
Add the OUT_FENCE_PTR property to writeback connectors, to enable
userspace to get a fence which will signal once the writeback is
complete. It is not allowed to request an out-fence without a
framebuffer attached to the connector.
A timeline is added to drm_writeback_connector for use by the writ
Mali-DP has a memory writeback engine which can be used to write the
composition result to a memory buffer. Expose this functionality as a
DRM writeback connector on supported hardware.
Changes since v1:
Daniel Vetter:
- Don't require a modeset when writeback routing changes
- Make writeback co
Writeback connectors represent writeback engines which can write the
CRTC output to a memory framebuffer. Add a writeback connector type and
related support functions.
Drivers should initialize a writeback connector with
drm_writeback_connector_init() which takes care of setting up all the
writeba
From: Liviu Dudau
Mali-DP display processors are able to write the composition result to a
memory buffer via the SE.
Add entry points in the HAL for enabling/disabling this feature, and
implement support for it on DP650 and DP550. DP500 acts differently and
so is omitted from this change.
Signe
this mail because:
You are the assignee for the bug.
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