Hi Linus,
I got a bit behind last week, so here is a delayed fixes pull,
A bunch of radeon/amd gpu fixes,
some nouveau regression fixes (ppc bios reading and runtime pm fix)
one drm core oops fix,
two qxl locking fixes,
one qxl regression fix,
Dave.
The following changes since commit f6702681a
ssignee for the bug.
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Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
> This phy driver is binded with the Rockchip DisplayPort
> driver, here are the brief properties:
> edp_phy: edp-phy at ff770274 {
> compatible = "rockchip,rk3288-dp-phy";
> rockchip,grf = <&grf>;
>
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rig
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
>> This phy driver is binded with the Rockchip DisplayPort
>> driver, here are the brief properties:
>> edp_phy: edp-phy at ff770274 {
>> compatible
Merged.
Thanks,
Inki Dae
2015ë
10ì 02ì¼ 09:30ì Joonyoung Shim ì´(ê°) ì´ ê¸:
> The arm_iommu_detach_device() is a function to detach device of iommu
> attached by arm_iommu_attach_device(). The exynos-drm uses
> arm_iommu_attach_device() so it should use arm_iommu_detach_device() to
>
Merged.
Thanks,
Inki Dae
2015ë
10ì 02ì¼ 09:33ì Joonyoung Shim ì´(ê°) ì´ ê¸:
> Struct of gem object in exynos_drm driver is struct exynos_drm_gem_obj.
> It's too long and we can know its meaning of name without _obj postfix.
>
> We use several names to variable name of gem object for e
Merged.
Thanks,
Inki Dae
2015ë
10ì 05ì¼ 12:04ì Joonyoung Shim ì´(ê°) ì´ ê¸:
> The commit d931589c01a2 ("drm/exynos: remove DRM_EXYNOS_GEM_MAP_OFFSET
> ioctl") removed it same with the ioctl that this patch adds. The reason
> that removed DRM_EXYNOS_GEM_MAP_OFFSET was we could use
> DR
Hi!
On 10/13/2015 12:35 AM, Dan Williams wrote:
> Per commit 2e586a7e017a "drm/vmwgfx: Map the fifo as cached" the driver
> expects the fifo registers to be cacheable. In preparation for
> deprecating ioremap_cache() convert its usage in vmwgfx to memremap().
>
> Cc: David Airlie
> Cc: Thomas He
On 10/13/2015 02:11 PM, Inki Dae wrote:
>
> Merged.
>
Thanks for merge but this will be conflicted with the patch of Daniel,
http://patchwork.freedesktop.org/patch/60565/
I found it on next-20151012, do you want v2 patch that DRM_UNLOCKED flag
is dropped?
Thanks.
> Thanks,
> Inki Dae
>
> 201
On 10/13/2015 02:23 PM, Joonyoung Shim wrote:
> On 10/13/2015 02:11 PM, Inki Dae wrote:
>>
>> Merged.
>>
>
> Thanks for merge but this will be conflicted with the patch of Daniel,
> http://patchwork.freedesktop.org/patch/60565/
>
Oops, wrong link,
http://lists.freedesktop.org/archives/intel-gfx
2015ë
10ì 13ì¼ 14:23ì Joonyoung Shim ì´(ê°) ì´ ê¸:
> On 10/13/2015 02:11 PM, Inki Dae wrote:
>>
>> Merged.
>>
>
> Thanks for merge but this will be conflicted with the patch of Daniel,
> http://patchwork.freedesktop.org/patch/60565/
Right. With Daniel patch, DRM_UNLOCKED flag isn't need
https://bugzilla.kernel.org/show_bug.cgi?id=105871
Bug ID: 105871
Summary: UVD decoder fails after hibernate
Product: Drivers
Version: 2.5
Kernel Version: 4.1.8
Hardware: x86-64
OS: Linux
Tree: Mainline
https://bugzilla.kernel.org/show_bug.cgi?id=105871
--- Comment #1 from Jose ---
Created attachment 190111
--> https://bugzilla.kernel.org/attachment.cgi?id=190111&action=edit
Full hibernate/resume log
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https://bugzilla.kernel.org/show_bug.cgi?id=105871
--- Comment #2 from Jose ---
I forgot to mention that as workaround a suspend/resume works, so it is only
the hibernate resume that triggers the bug.
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gmail.com ---
Tested on 11.0.2 and still it freezes
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This introduces new functions to allocate/free buffer using DMA mapping
API. Now already exynos-drm uses DMA mapping API to allocate/free buffer
but it is used on both iommu and non-iommu, so split it. It will be
added new buffer allocation not to use DMA mapping API later.
Signed-off-by: Joonyoun
Hi,
This patchset is about gem codes update of exynos-drm.
The first and second patches are cleanup to remove useless codes.
The rest is to support cachable gem allocation.
The exynos-drm uses DMA mapping API to allocate/mmap buffer of gem. If
it is cachable, does it with DMA_ATTR_NON_CONSISTENT
This eliminates declaration of functions that is removed by the
commit 63540f01917c ("[media] drm/exynos: Convert
g2d_userptr_get_dma_addr() to use get_vaddr_frames()") and eliminate
vma_is_io() that isn't used anywhere now.
Also remove exynos_gem_get_pages() and exynos_drm_gem_userptr_ioctl(),
th
It doesn't care whether memory is continuous physically if iommu is
supported but we will always use EXYNOS_BO_CONTIG flag on iommu, so it
can mean that the memory is continuous memory for device.
Signed-off-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_fb.c| 32 --
DMA_ATTR_NON_CONSISTENT isn't supported in DMA mapping API of ARM, so
it doesn't give any effects to use non-consistent DMA attribute.
Signed-off-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/d
This introduces new functions to allocate/free buffer using
drm_gem_get/put_pages() instead of DMA mapping API. They also use sg
list to manage pages.
Signed-off-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 48 +
drivers/gpu/drm/exynos/exynos_d
There is no reason to be wapper functions to use DMA mapping APIs. We
can use directly DMA mapping APIs without locking and remove the wapper
functions.
Signed-off-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 10 +-
drivers/gpu/drm/exynos/exynos_drm_gem.c | 26 ---
This adds necessary two ioctls for cpu access of gem object from user.
It needs to be synced properly in order for the cpu and device if the
buffer of gem object is cachable.
- DRM_IOCTL_EXYNOS_GEM_CPU_PREP
Should be used explicitly before it will be cpu access of gem object
from user.
- DRM_IOCT
The buffer allocation using DMA mapping API can't support non-continuous
buffer on non-iommu and cachable buffer, so switch to new buffer
allocation using drm_gem_get/put_pages() and doesn't use DMA mapping API
for mmap except allocation of physically continuous buffer on non-iommu.
Signed-off-by:
The dma_addr of gem will be DMA_ERROR_CODE if gem is created and
will keep DMA_ERROR_CODE if gem has EXYNOS_BO_NONCONTIG flag on
non-iommu.
Signed-off-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
d
ttp://lists.freedesktop.org/archives/dri-devel/attachments/20151013/de0ed9a1/attachment.html>
On Mon, Oct 12, 2015 at 10:57:43AM +0200, Lukas Wunner wrote:
> Commit 599bbb9de0fe ("drm/i915: i915 cannot provide switcher services.")
> removed all remaining vga_switcheroo symbols from intel_acpi.c but left
> the include. Drop it.
>
> Signed-off-by: Lukas Wunner
Queued for -next, thanks for
On Mon, 12 Oct 2015, Lukas Wunner wrote:
> Commit 599bbb9de0fe ("drm/i915: i915 cannot provide switcher services.")
> removed all remaining vga_switcheroo symbols from intel_acpi.c but left
> the include. Drop it.
>
> Signed-off-by: Lukas Wunner
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/d
On Mon, Oct 12, 2015 at 12:09:53PM -0400, Alex Deucher wrote:
> On Fri, Aug 28, 2015 at 7:30 AM, Lukas Wunner wrote:
> > Signed-off-by: Lukas Wunner
> Reviewed-by: Alex Deucher
Merged the 3 cleanup patches to drm-misc.
-Daniel
>
> > ---
> > drivers/gpu/vga/vga_switcheroo.c | 17 +
On Mon, Oct 12, 2015 at 05:10:20PM -0400, Alex Deucher wrote:
> On Mon, Oct 12, 2015 at 5:07 PM, Alex Deucher
> wrote:
> > On Fri, Aug 14, 2015 at 12:18 PM, Lukas Wunner wrote:
> >> Originally by Seth Forshee , 2012-10-04:
> >> The gmux allows muxing the DDC independently from the display, s
The commit "drm/vmwgfx: Fix up user_dmabuf refcounting", while fixing a
kernel crash introduced a NULL pointer dereference on older hardware.
Fix this.
Cc:
Signed-off-by: Thomas Hellstrom
Reviewed-by: Sinclair Yeh
Reviewed-by: Brian Paul
---
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 3 ++-
1
On Mon, Oct 12, 2015 at 09:12:57PM +, Williams, Dan J wrote:
> On Mon, 2015-10-12 at 09:01 +0200, Daniel Vetter wrote:
> > On Fri, Oct 09, 2015 at 06:16:25PM -0400, Dan Williams wrote:
> > > i915 expects the OpRegion to be cached (i.e. not __iomem), so explicitly
> > > map it with memremap rath
On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
> On Mon, 12 Oct 2015 09:04:20 +0200,
> Daniel Vetter wrote:
> >
> > Another pile of regressions for Jairo to track ...
> >
> > On Sat, Oct 10, 2015 at 11:46:29AM +0200, Takashi Iwai wrote:
> > > Hi,
> > >
> > > I noticed that a HSW l
On Tue, Oct 13, 2015 at 04:00:45PM +0900, Joonyoung Shim wrote:
> Hi,
>
> This patchset is about gem codes update of exynos-drm.
>
> The first and second patches are cleanup to remove useless codes.
> The rest is to support cachable gem allocation.
>
> The exynos-drm uses DMA mapping API to allo
Am Mittwoch, den 30.09.2015, 09:53 +0200 schrieb Christian Gmeiner:
> Hi Lucas,
>
> 2015-09-28 12:39 GMT+02:00 Lucas Stach :
> > Hi Christian,
> >
> > Am Montag, den 28.09.2015, 11:46 +0200 schrieb Christian Gmeiner:
> >> Hi Lucas.
> >>
> >> I think I have run into a cache flush / cache coherency
On 10/13/2015 05:27 PM, Daniel Vetter wrote:
> On Tue, Oct 13, 2015 at 04:00:45PM +0900, Joonyoung Shim wrote:
>> Hi,
>>
>> This patchset is about gem codes update of exynos-drm.
>>
>> The first and second patches are cleanup to remove useless codes.
>> The rest is to support cachable gem allocatio
On Tue, Oct 13, 2015 at 10:24:58AM +0200, Daniel Vetter wrote:
> On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
> > On Mon, 12 Oct 2015 09:04:20 +0200,
> > Daniel Vetter wrote:
> > >
> > > Another pile of regressions for Jairo to track ...
> > >
> > > On Sat, Oct 10, 2015 at 11:46:
On 10/13/2015 05:37 PM, Joonyoung Shim wrote:
> On 10/13/2015 05:27 PM, Daniel Vetter wrote:
>> On Tue, Oct 13, 2015 at 04:00:45PM +0900, Joonyoung Shim wrote:
>>> Hi,
>>>
>>> This patchset is about gem codes update of exynos-drm.
>>>
>>> The first and second patches are cleanup to remove useless c
Add myself as the maintainer of the atmel-hlcdc DRM driver.
Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
---
Changes since v1:
- Fix the MAINTAINER entry title
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 797236b..670ff22
Exynos GEM objects contains an array of pointers to the pages, which the
allocated buffer consists of. Till now the code used some hacks (like
relying on DMA-mapping internal structures or using ARM-specific
dma_to_pfn helper) to build this array. This patch fixes this by adding
proper call to dma_
Thanks for the review Rob.
Regards
Shashank
On 10/12/2015 11:38 PM, Rob Bradford wrote:
> On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
>> BDW/SKL/BXT supports Degamma color correction feature, which
>> linearizes the non-linearity due to gamma encoded color values.
>> This will be app
Hi Marek,
On 10/13/2015 07:22 PM, Marek Szyprowski wrote:
> Exynos GEM objects contains an array of pointers to the pages, which the
> allocated buffer consists of. Till now the code used some hacks (like
> relying on DMA-mapping internal structures or using ARM-specific
> dma_to_pfn helper) to bu
Regards
Shashank
On 10/12/2015 11:39 PM, Rob Bradford wrote:
> On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
>> BDW/SKL/BXT platforms support various Gamma correction modes
>> which are:
>> 1. Legacy 8-bit mode
>> 2. 10-bit Split Gamma mode
>> 3. 12-bit mode
>>
>> This patch does the f
Regards
Shashank
On 10/12/2015 11:43 PM, Rob Bradford wrote:
> On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
>> I915 color manager registers pipe degamma correction as palette
>> correction before CTM, DRM property.
>>
>> This patch adds the no of coefficients(65) for degamma correctio
Exynos GEM objects contains an array of pointers to the pages, which the
allocated buffer consists of. Till now the code used some hacks (like
relying on DMA-mapping internal structures or using ARM-specific
dma_to_pfn helper) to build this array. This patch fixes this by adding
proper call to dma_
On 10/6/2015 2:12 PM, Michel Thierry wrote:
> On 10/5/2015 7:06 PM, Kristian Høgsberg wrote:
>> On Mon, Oct 5, 2015 at 7:03 AM, Michel Thierry
>> wrote:
>>> On 9/14/2015 2:54 PM, MichaÅ Winiarski wrote:
On Thu, Sep 03, 2015 at 03:23:58PM +0100, Michel Thierry wrote:
>
> Gen8+ s
On Tue, 13 Oct 2015, Ville Syrjälä wrote:
> On Tue, Oct 13, 2015 at 10:24:58AM +0200, Daniel Vetter wrote:
>> On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
>> > On Mon, 12 Oct 2015 09:04:20 +0200,
>> > Daniel Vetter wrote:
>> > >
>> > > Another pile of regressions for Jairo to t
On Tue, Oct 13, 2015 at 06:32:53PM +0900, Joonyoung Shim wrote:
> On 10/13/2015 05:37 PM, Joonyoung Shim wrote:
> > On 10/13/2015 05:27 PM, Daniel Vetter wrote:
> >> On Tue, Oct 13, 2015 at 04:00:45PM +0900, Joonyoung Shim wrote:
> >>> Hi,
> >>>
> >>> This patchset is about gem codes update of exyn
This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
Color Management is an extension to DRM framework. It allows
abstraction of hardware color correction and enhancement capabilities
by virtue of DRM properties.
There are two major types of color correction supported by DRM
color manager:
- CTM: color transformation matrix, properties where a corre
DRM color management is written to extract the color correction
capabilities of various platforms, and every platform can showcase
its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette
correction. Also the correction can be applied after
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/drm_ato
As per DRM color manager design, if a userspace wants to set a correction
blob, it prepares it and sends the blob_id to kernel via set_property
call. DRM framework takes this blob_id, gets the blob, and saves it
in the CRTC state, so that, during the atomic_commit, the color correction
values from
As per the DRM get_property implementation for a blob, framework
is supposed to return the blob_id to the caller. All the color
management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management
properties, by referring to the existing blob for
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/uapi/drm/drm.h | 26 +++
Color Manager framework defines a DRM property for color
space transformation and Gamut mapping. This property is called
CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for co
This patch adds set property interface for intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma
>From DRM color management:
DRM color manager supports these color properties:
1. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
2. "palette_before_ctm": for corrections which get
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_after_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeffi
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_before_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeff
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction macr
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2.
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
Signed-of
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. Split mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(512) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma
Si
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
2
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
Signed-off-by:
On 10 October 2015 at 05:55, Sharma, Shashank
wrote:
> On 10/10/2015 4:17 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:28, Shashank Sharma
>> wrote:
>> [snip]
>>>
>>> +
>>> +/* Color management bit utilities */
>>> +#define GET_BIT_MASK(n) ((1 << n) - 1)
>>> +
>>> +/*
On 10 October 2015 at 06:01, Sharma, Shashank
wrote:
> On 10/10/2015 3:51 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> From DRM color management:
>>>
>>> DRM color manager supports these color propert
On 10 October 2015 at 06:09, Sharma, Shashank
wrote:
> On 10/10/2015 4:37 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> CHV/BSW platform supports two different pipe level gamma
>>> correction modes, which are:
>>> 1. Legacy 8-bit m
On 10 October 2015 at 06:20, Sharma, Shashank
wrote:
> On 10/10/2015 4:54 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> The color correction blob values are loaded during set_property
>>> calls. This patch adds a function to find t
On 10 October 2015 at 06:21, Sharma, Shashank
wrote:
> On 10/10/2015 5:09 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
[snip]
>>> + switch (num_samples) {
>>> + case GAMMA_DISABLE_VALS:
>>> +
>>> + /* Disable Gamma functio
On Fri, Oct 9, 2015 at 4:27 PM, Eric Anholt wrote:
> VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
> other Broadcom SoCs.
>
> This binding follows the model of msm, imx, sti, and others, where
> there is a subsystem node for the whole GPU, with nodes for the
The subsystem
On Thu, Oct 8, 2015 at 3:27 AM, Thierry Reding
wrote:
> On Wed, Oct 07, 2015 at 11:00:51PM +0200, Maciej S. Szmigiero wrote:
>> This patch adds DT bindings for United Radiant Technology
>> UMSH-8596MD-xT 7.0" WVGA TFT LCD panels.
>>
>> Signed-off-by: Maciej Szmigiero
>> ---
>> Documentation/dev
On 10 October 2015 at 06:26, Sharma, Shashank
wrote:
> On 10/10/2015 5:13 AM, Emil Velikov wrote:
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
>>> that needs to be programmed into CGM (Color Gamut Mapping) re
Thanks for the review Emil.
Please find my comments inline
Regards
Shashank
On 10/13/2015 6:29 PM, Emil Velikov wrote:
> On 10 October 2015 at 05:55, Sharma, Shashank
> wrote:
>> On 10/10/2015 4:17 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:28, Shashank Sharma
Regards
Shashank
On 10/13/2015 6:33 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:01, Sharma, Shashank
> wrote:
>> On 10/10/2015 3:51 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
>>> wrote:
From DRM color management:
On 10 October 2015 at 06:31, Sharma, Shashank
wrote:
> On 10/10/2015 5:19 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> BDW/SKL/BXT supports Degamma color correction feature, which
>>> linearizes the non-linearity due to gamma enco
Regards
Shashank
On 10/13/2015 6:38 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:09, Sharma, Shashank
> wrote:
>> On 10/10/2015 4:37 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
>>> wrote:
CHV/BSW platform supports two differen
On 10 October 2015 at 06:34, Sharma, Shashank
wrote:
> On 10/10/2015 5:24 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
>>> that needs to be programmed into respec
Regards
Shashank
On 10/13/2015 6:47 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:20, Sharma, Shashank
> wrote:
>> On 10/10/2015 4:54 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
>>> wrote:
The color correction blob values are l
Regards
Shashank
On 10/13/2015 6:53 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:21, Sharma, Shashank
> wrote:
>> On 10/10/2015 5:09 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
> [snip]
+ switch (num_samples) {
+ c
Regards
Shashank
On 10/13/2015 7:03 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:26, Sharma, Shashank
> wrote:
>> On 10/10/2015 5:13 AM, Emil Velikov wrote:
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
>>> wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 m
bug.
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Regards
Shashank
On 10/13/2015 7:15 PM, Emil Velikov wrote:
> On 10 October 2015 at 06:34, Sharma, Shashank
> wrote:
>> On 10/10/2015 5:24 AM, Emil Velikov wrote:
>>>
>>> Hi Shashank,
>>>
>>> On 9 October 2015 at 20:29, Shashank Sharma
>>> wrote:
BDW/SKL/BXT support Color Space Conver
On 13 October 2015 at 14:36, Sharma, Shashank
wrote:
> On 10/13/2015 6:33 PM, Emil Velikov wrote:
>>
>> On 10 October 2015 at 06:01, Sharma, Shashank
>> wrote:
>>>
>>> On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
>>
On 13 October 2015 at 14:40, Sharma, Shashank
wrote:
> I am not sure if I915 follows a general rule of using for(...) over while(),
> coz I see many instances of using a while in i915_gem, i915_drv, i915_irq
> etc, so it should be good. I would see if someone else can suggest another
> good reas
> Do you have a link handy ? I suspect that something else was mentioned in
> that comment as splitting function declaration and definition is extremely
> uncommon
Yep, maybe I misunderstood. I will add the definition here.
Regards
Shashank
-Original Message-
From: Emil Velikov [mailto:
Regards
Shashank
On 10/13/2015 7:29 PM, Emil Velikov wrote:
> On 13 October 2015 at 14:40, Sharma, Shashank
> wrote:
>
>> I am not sure if I915 follows a general rule of using for(...) over while(),
>> coz I see many instances of using a while in i915_gem, i915_drv, i915_irq
>> etc, so it should
On 13 October 2015 at 13:16, Michel Thierry wrote:
> On 10/6/2015 2:12 PM, Michel Thierry wrote:
>>
>> On 10/5/2015 7:06 PM, Kristian Høgsberg wrote:
>>>
>>> On Mon, Oct 5, 2015 at 7:03 AM, Michel Thierry
>>> wrote:
On 9/14/2015 2:54 PM, MichaÅ Winiarski wrote:
>
>
> On Th
Drop unused drm_atomic and fix comment for drm_debug.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_drv.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 53d09a1..3a8d598 100644
--- a/drivers/gpu/drm/drm_drv.c
Add a new drm_debug bit for turning on DPCD logging, to aid debugging
with troublesome monitors.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_dp_helper.c | 66 -
include/drm/drmP.h | 6
2 files changed, 58 insertions(+), 14 deletions
On Tue, 13 Oct 2015, Rob Clark wrote:
> Add a new drm_debug bit for turning on DPCD logging, to aid debugging
> with troublesome monitors.
I wish you could find some balance between having the error cases logged
with normal kms debugging vs. having to have full blown aux traffic
debugging to noti
On Tue, Oct 13, 2015 at 10:30 AM, Jani Nikula
wrote:
> On Tue, 13 Oct 2015, Rob Clark wrote:
>> Add a new drm_debug bit for turning on DPCD logging, to aid debugging
>> with troublesome monitors.
>
> I wish you could find some balance between having the error cases logged
> with normal kms debugg
Signed-off-by: Michal Hrbek
---
drivers/gpu/vga/vgaarb.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c
index a0b4334..41f3e13 100644
--- a/drivers/gpu/vga/vgaarb.c
+++ b/drivers/gpu/vga
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