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On Fri, May 8, 2015 at 5:24 PM, Peter Zijlstra wrote:
> On Thu, May 07, 2015 at 03:15:43PM +0100, Robert Bragg wrote:
>
>> I've changed the uapi for configuring the i915_oa specific attributes
>> when calling perf_event_open(2) whereby instead of cramming lots of
>> bitfields into the perf_event_a
Hi Linus,
radeon, one oops fix, one bug fix, one pci id addition patch
i915, one suspend/resume regression fix.
all seems quiet enough.
Dave.
The following changes since commit 030bbdbf4c833bc69f502eae58498bc5572db736:
Linux 4.1-rc3 (2015-05-10 15:12:29 -0700)
are available in the git repo
On Thu, 14 May 2015, Liu Ying wrote:
> This patch adds a helper to get bits per pixel value of MIPI DSI pixel format.
> The helper takes a parameter in the type 'enum mipi_dsi_pixel_format' and
> returns it's bits per pixel value if the parameter is valid, otherwise, it
> returns -EINVAL. The hel
dma_alloc_coherent() can return memory in the vmalloc range.
virt_to_page() cannot handle such addresses and crashes. This
patch detects such cases and obtains the struct page * using
vmalloc_to_page() instead.
Signed-off-by: Alexandre Courbot
---
This patch is a follow-up of the following discus
On 05/13/15 20:42, Jean-Francois Moine wrote:
> On Wed, 13 May 2015 12:23:45 +0300
> Jyri Sarha wrote:
>
>> Jean-Francois, would you consider trying the generic ASoC patch with
>> your HW, as I can not test the spdif functionality with mine?
>
> Hi Jyri,
>
> I am not sure to need all the stuff you
On 15.05.2015 12:52, Dave Jones wrote:
>
> The only remaining problem is there are some visible glitches, mostly
> noticable
> while scrolling a terminal.
What kind of glitches? If it's tearing, with current xf86-video-ati Git
you can try Option "TearFree".
--
Earthling Michel Dänzer
rivers/gpu/drm/bridge/ptn3460.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Thierry
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Hello,
I've just tested 'modetest' with the fix applied, and while the nullptr
deference goes away, I now get a division by zero.
modetest output:
Encoders:
id crtctypepossible crtcs possible clones
22 0 TMDS0x0001 0x
30 29 TMDS0x00
Re-pinging Marteen on an email address that still exists :P
On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot wrote:
> On Sun, Mar 15, 2015 at 5:41 PM, Alexandre Courbot
> wrote:
>> On 03/14/2015 04:33 AM, Maarten Lankhorst wrote:
>>>
>>> Hey,
>>>
>>> Op 13-03-15 om 07:27 schreef Alexandre Cou
ch more
appropriate solution.
Thierry
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Hello,
I did another run with drm.debug=0xff and also tried to figure out where
the div-by-zero comes from.
The only division I see is in fimd_calc_clkdiv() (which is called by
fimd_commit()). So it looks like 'ideal_clk' is zero when calling
DIV_ROUND_UP().
'htotal' and 'vtotal' can't be zer
On Fri, May 15, 2015 at 06:16:59PM +0900, Michel Dänzer wrote:
> On 15.05.2015 12:52, Dave Jones wrote:
> >
> > The only remaining problem is there are some visible glitches, mostly
> > noticable
> > while scrolling a terminal.
>
> What kind of glitches? If it's tearing, with current xf8
elp the reliability any?
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nee for the bug.
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DSI PLL driver can work with common clock framework and provide source of DSI
byte clock and pixel clock, as a clock provider.
Hai Li (3):
drm/msm/dsi: Add DSI PLL clock driver support
drm/msm/dsi: Enable PLL driver in MSM DSI
drm/msm/dsi: Separate PHY to another platform device
Documentat
DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.
This change handles DSI 28nm PLL only.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
Signed-off-by: Stephane Viau
Signed-off-by: Wentao Xu
---
drivers
This change activates PLL driver for DSI to work with
common clock framework.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.c | 14 +++
drivers/gpu/drm/msm/dsi/dsi.h | 43 ---
drivers/gpu/drm/msm/dsi/dsi_host.c| 60 ++
drive
There are different types of PHY from one chipset to another, while
the DSI host controller is relatively consistent across platforms.
Also, the PLL inside PHY is providing the source of DSI byte and
pixel clocks, which are used by DSI host controller. Separated devices
for clock provider and clock
.
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Sorry for lagging on this a bit (been a bit distracted bring up a new
device and other things). Here are the set of fixes for the next
4.1-rc
BR,
-R
The following changes since commit 332545b3016cbff066c17037d32ec8aae8e4cfb5:
Merge tag 'drm-intel-fixes-2015-05-08' of
git://anongit.freedesktop
From: Gustavo Padovan
old_plane_state is already assigned to old_state->plane_states[i] inside
for_each_plane_in_state(). Here we remove an the extra assignment.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/drm_atomic_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/
On Fri, May 15, 2015 at 04:09:54PM +0900, Alexandre Courbot wrote:
> dma_alloc_coherent() can return memory in the vmalloc range.
> virt_to_page() cannot handle such addresses and crashes. This
> patch detects such cases and obtains the struct page * using
> vmalloc_to_page() instead.
>
> Signed-o
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Op 15-05-15 om 09:11 schreef Alexandre Courbot:
> Re-pinging Marteen on an email address that still exists :P
>
> On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot
> wrote:
>> On Sun, Mar 15, 2015 at 5:41 PM, Alexandre Courbot
>> wrote:
>>> On 03/14/2015 04:33 AM, Maarten Lankhorst wrote:
2015-05-15 15:09 GMT+08:00 Alexandre Courbot :
> dma_alloc_coherent() can return memory in the vmalloc range.
> virt_to_page() cannot handle such addresses and crashes. This
> patch detects such cases and obtains the struct page * using
> vmalloc_to_page() instead.
>
> Signed-off-by: Alexandre Cour
Hi Stephen,
Adding Mikko in the loop (after all, he was the one complaining about
this signed long limitation in the first place, and I forgot to add
him in the Cc list :-/).
Mikko, are you okay with the approach proposed by Stephen (adding a
new method) ?
On Thu, 7 May 2015 09:37:02 +0200
Boris
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