2011/12/7 Rafa? Mi?ecki :
> W dniu 7 grudnia 2011 15:53 u?ytkownik Alex Deucher
> napisa?:
>> 2011/12/7 Rafa? Mi?ecki :
>>> W dniu 7 grudnia 2011 14:53 u?ytkownik Alex Deucher
>>> napisa?:
2011/12/7 Rafa? Mi?ecki :
> In theory function atombios_get_encoder_mode should report
> ATOM_E
This set of patches removes psb_intel_output and replaces it with
psb_intel_encoder and psb_intel_connector. It also replaces the SDVO code with a
slightly modified version from i915. i915 SDVO needs Intel gmbus so this is
added along with a SDVO DDC bus guessing fix for Poulsbo.
Patrik Jakobsson
First step towards adding i915 alike encoder and connector abstractions. This
will make life easier when adding i915 output code into our driver. It also
removes the old psb_intel_output struct.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/psb_intel_display.c |7 +
drivers/
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/psb_intel_drv.h |5 +++--
drivers/gpu/drm/gma500/psb_intel_modes.c | 16 +++-
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h
b/drivers/gpu/drm/gma500/psb_intel_
Fix cases where we need to know what encoder type is behind a given connector.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/framebuffer.c |8
drivers/gpu/drm/gma500/psb_drv.c |6 +++---
drivers/gpu/drm/gma500/psb_intel_display.c | 24 -
LVDS for PSB now uses psb_intel_encoder and psb_intel_connectors instead of
psb_intel_output. i2c_bus and ddc_bus are moved to lvds_priv. There was also a
pointer to mode_dev (for no obvious reason) that we now get directly from
dev_priv.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma50
Before we integrate the new SDVO code we need GMBUS support
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/Makefile|1 +
drivers/gpu/drm/gma500/intel_gmbus.c | 493
drivers/gpu/drm/gma500/psb_device.c|7 +
drivers/gpu/drm/gma500
Replace psb_intel_output with psb_intel_encoder and psb_intel_connector.
Things will need to be cleaned up and tested so consider this an initial
patch for Cedarview.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/cdv_intel_crt.c | 47 +++-
drivers/gpu/drm/gma500/cdv_in
Our current SDVO implementation is not working properly, so replace it with
a modified version of the i915. Further testing and debugging is needed to make
sure we can handle the different SDVO setups and wiring.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/psb_drv.h |
Replace psb_intel_output with psb_intel_encoder and psb_intel_connector
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/oaktrail_crtc.c | 18
drivers/gpu/drm/gma500/oaktrail_hdmi.c | 29 +++
drivers/gpu/drm/gma500/oaktrail_lvds.c | 79 +--
We currently don't have support for parsing SDVO mappings from BIOS so we're
guessing the bus switch parameter. This isn't working so hardcode it to a
configuration known to work on most poulsbo hardware.
Signed-off-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/psb_intel_sdvo.c |8
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,25 @@ typedef struct _drmModeConnector {
uint32_t *encoders; /**< List of encoder ids */
} drmModeConnector, *drmModeConnectorPtr;
+typedef struct _drmModePlane {
+ uint32_t count_formats;
+ uint32_t *formats;
+ uint32_t plane_id;
+ uint32_t crtc_id;
+ uint32_t fb_id;
+
+ uint32_t crtc_x, crtc_y;
+ uint32_t x, y;
+
+ uint32_t possible_crtcs;
+ uint32_t gamma_size;
+} drmModePlane, *drmModePlanePtr;
+
+typedef struct _drmModePlaneRes {
+ uint32_t count_planes;
+ uint32_t *planes;
+} drmModePlaneRes, *drmModePlaneResPtr;
extern void drmModeFreeModeInfo( drmModeModeInfoPtr ptr );
extern void drmModeFreeResources( drmModeResPtr ptr );
@@ -286,6 +304,7 @@ extern void drmModeFreeFB( drmModeFBPtr ptr );
extern void drmModeFreeCrtc( drmModeCrtcPtr ptr );
extern void drmModeFreeConnector( drmModeConnectorPtr ptr );
extern void drmModeFreeEncoder( drmModeEncoderPtr ptr );
+extern void drmModeFreePlane( drmModePlanePtr ptr );
/**
* Retrives all of the resources associated with a card.
@@ -307,6 +326,11 @@ extern drmModeFBPtr drmModeGetFB(int fd, uint32_t
bufferId);
extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
uint8_t bpp, uint32_t pitch, uint32_t bo_handle,
uint32_t *buf_id);
+/* ...with a specific pixel format */
+extern int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
+uint32_t pixel_format, uint32_t bo_handles[4],
+uint32_t pitches[4], uint32_t offsets[4],
+uint32_t *buf_id, uint32_t flags);
/**
* Destroies the given framebuffer.
*/
@@ -391,6 +415,15 @@ extern int drmModeCrtcGetGamma(int fd, uint32_t crtc_id,
uint32_t size,
extern int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id,
uint32_t flags, void *user_data);
+extern drmModePlaneResPtr drmModeGetPlaneResources(int fd);
+extern drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id);
+extern int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id,
+ uint32_t fb_id, uint32_t flags,
+ uint32_t crtc_x, uint32_t crtc_y,
+ uint32_t crtc_w, uint32_t crtc_h,
+ uint32_t src_x, uint32_t src_y,
+ uint32_t src_w, uint32_t src_h);
+
#if defined(__cplusplus) || defined(c_plusplus)
}
#endif
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https://bugs.freedesktop.org/show_bug.cgi?id=43395
--- Comment #13 from Tomas Schlosser 2011-12-07
13:33:53 PST ---
(In reply to comment #12)
> Does setting the environment variable vblank_mode=0 for the Wine process using
> OpenGL work around the problem? There should be a message
>
> ATTENTI
Signed-off-by: Rafa? Mi?ecki
---
drivers/gpu/drm/radeon/r600_hdmi.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c
b/drivers/gpu/drm/radeon/r600_hdmi.c
index 5021372..06f923e 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
++
Signed-off-by: Rafa? Mi?ecki
---
drivers/gpu/drm/radeon/evergreen.c | 14 ++
drivers/gpu/drm/radeon/evergreen_reg.h |8
drivers/gpu/drm/radeon/r600_audio.c| 22 +++---
3 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
Signed-off-by: Rafa? Mi?ecki
---
drivers/gpu/drm/radeon/evergreen_reg.h | 10 +++
drivers/gpu/drm/radeon/r600_hdmi.c | 44 ++--
2 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h
b/drivers/gpu/drm/radeon
Signed-off-by: Rafa? Mi?ecki
---
drivers/gpu/drm/radeon/atombios_encoders.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 39c04c1..63e5426 100644
--- a/drivers/gpu/drm/r
2011/12/7 Rafa? Mi?ecki :
>
> Signed-off-by: Rafa? Mi?ecki
> ---
> ?drivers/gpu/drm/radeon/atombios_encoders.c | ? ?6 +++---
> ?1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
> b/drivers/gpu/drm/radeon/atombios_encoders.c
> index 39c04
2011/12/7 Alex Deucher :
> 2011/12/7 Rafa? Mi?ecki :
>>
>> Signed-off-by: Rafa? Mi?ecki
>> ---
>> ?drivers/gpu/drm/radeon/atombios_encoders.c | ? ?6 +++---
>> ?1 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
>> b/drivers/gpu/drm/radeo
2011/12/7 Rafa? Mi?ecki :
>
> Signed-off-by: Rafa? Mi?ecki
> ---
> ?drivers/gpu/drm/radeon/evergreen_reg.h | ? 10 +++
> ?drivers/gpu/drm/radeon/r600_hdmi.c ? ? | ? 44
> ++--
> ?2 files changed, 46 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeo
There's no reason to force the first byte to be correct if we're already
scoring how correct the header is.
See also: https://bugzilla.redhat.com/show_bug.cgi?id=722909
Signed-off-by: Adam Jackson
---
drivers/gpu/drm/drm_edid.c | 18 --
1 files changed, 8 insertions(+), 10 del
When 2 or more EDID extension blocks are present, segment must be
selected prior to reading the extended EDID block over the DDC
channel. Add support for this.
Signed-off-by: Jean Delvare
Cc: Adam Jackson
---
This needs testing by someone with access to such a display.
drivers/gpu/drm/drm_edid
On 02.12.11 21:48:20, Markus Trippelsdorf wrote:
> BTW I always see (mostly only on screen, sometimes in the logs):
>
> [Firmware Bug]: cpu 2, try to use APIC500 (LVT offset 0) for vector 0x10400,
> but the register is already in use for vector 0xf9 on another cpu
> [Firmware Bug]: cpu 2, IBS int
he connected
HDMI monitor. Currently only the 3D format support fields are read.
Later this could be extended. This information is expected to be sent to
the user space which then sets the format on the monitor.
This patch also handles DIP register signaling to the HDMI connected 3D
monitor th
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