https://bugs.freedesktop.org/show_bug.cgi?id=29579
--- Comment #19 from Juho-Mikko Pellinen
2010-08-18 00:35:06 PDT ---
AGP is not explicitly loaded, but it's initialization messages appear two
seconds before any drm messages. During boot radeon is loaded just before
fbcon.
Adding agpgart and a
https://bugs.freedesktop.org/show_bug.cgi?id=29556
--- Comment #17 from Andy Furniss 2010-08-18
03:20:48 PDT ---
(In reply to comment #0)
> Created an attachment (id=37840)
--> (https://bugs.freedesktop.org/attachment.cgi?id=37840)
> system dmesg
>
> Using latest git (as of 12/08/2010) of libd
Alex Deucher wrote:
Does reverting this part of the patch fix it?
@@ -1055,10 +1055,10 @@ static void r600_texture_size(unsigned nfaces,
unsigned blevel, unsigned nlevels
}
*l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
*mipmap_size = offset;
- if (!blevel)
-
Andy Furniss wrote:
No, it does make the nunbers bigger, though -
radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
1048576 have 1409024)
Further (non exhaustive) testing shows it regresses some mesa demos as
well - lodbias,reflect & shadowtex -
mipmap bo too small (256 2
On Wed, Aug 18, 2010 at 7:45 AM, Andy Furniss wrote:
> Andy Furniss wrote:
>
>> No, it does make the nunbers bigger, though -
>>
>> radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
>> 1048576 have 1409024)
>
> Further (non exhaustive) testing shows it regresses some mesa demos as
Alex Deucher wrote:
On Wed, Aug 18, 2010 at 7:45 AM, Andy Furniss wrote:
Andy Furniss wrote:
No, it does make the nunbers bigger, though -
radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
1048576 have 1409024)
Further (non exhaustive) testing shows it regresses some mesa
Asics that use an AGP to PCIE bridge don't have the AGP_STATUS
register so just use whatever mode the host side setup.
Signed-off-by: Alex Deucher
Cc: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_agp.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/gp
https://bugs.freedesktop.org/show_bug.cgi?id=29652
Summary: Git commit
Product: Mesa
Version: git
Platform: Other
OS/Version: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/R600
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #2 from Sven Arvidsson 2010-08-18 11:56:54 PDT ---
It seems to have regressed after the glsl2 merge it fails with "0:4(2):
preprocessor error: Invalid tokens after #" for both shaders.
/* Shader 2 source, checksum 0 */
#version 120
Last known good: 2.6.35
Failing kernel: 2.6.36-rc1
During boot kernel display this message:
[0.831906] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for plane,
expect flickering: entries required = 36, available = 28.
[0.895058] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for
https://bugs.freedesktop.org/show_bug.cgi?id=29652
Jon Severinsson changed:
What|Removed |Added
Summary|Git commit |Git commit e62e5b0 breaks
On Wed, 18 Aug 2010 20:46:37 +0200, Maciej Rutecki
wrote:
> Last known good: 2.6.35
> Failing kernel: 2.6.36-rc1
>
> During boot kernel display this message:
> [0.831906] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for plane,
> expect flickering: entries required = 36, available = 28
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #3 from Marek Olšák 2010-08-18 12:37:15 PDT ---
Could you please file a new bug against the GLSL2 compiler (Mesa core, I guess)
to keep driver-specific and core bugs separate?
--
Configure bugmail: https://bugs.freedesktop.org/userp
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #4 from Marek Olšák 2010-08-18 12:39:08 PDT ---
Other than that, dynamic branching and loops should work with r300g to my
knowledge, I recall Tom adding the support for it just recently.
--
Configure bugmail: https://bugs.freedeskto
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #5 from Sven Arvidsson 2010-08-18 13:14:40 PDT ---
Filed as bug 29654
--
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
You are the assignee for the bug.
https://bugs.freedesktop.org/show_bug.cgi?id=28771
--- Comment #24 from Sven Arvidsson 2010-08-18 13:22:16 PDT ---
I compared how Intel (i965) compares when it comes to DRI2 and vsync, and as
far as I can tell they have the same problems (needs a special driver="dri2"
stansa in drirc, toggling vs
https://bugs.freedesktop.org/show_bug.cgi?id=29658
Summary: Crash when starting "spring rts" the system freeze:
/usr/lib/dri/r600_dri.so(radeon_bo_legacy_validate+0x4
83)
Product: Mesa
Version: unspecified
Platform:
From: Ben Skeggs
Nouveau will need this on GeForce 8 and up to account for the GPU
reordering physical VRAM for some memory types.
v2: rebase to include nvc0_instmem.c changes
Signed-off-by: Ben Skeggs
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 12 ++-
drivers/gpu/drm/nouveau/nouveau_
https://bugs.freedesktop.org/show_bug.cgi?id=29579
--- Comment #19 from Juho-Mikko Pellinen
2010-08-18 00:35:06 PDT ---
AGP is not explicitly loaded, but it's initialization messages appear two
seconds before any drm messages. During boot radeon is loaded just before
fbcon.
Adding agpgart and a
https://bugs.freedesktop.org/show_bug.cgi?id=29556
--- Comment #17 from Andy Furniss 2010-08-18
03:20:48 PDT ---
(In reply to comment #0)
> Created an attachment (id=37840)
--> (https://bugs.freedesktop.org/attachment.cgi?id=37840)
> system dmesg
>
> Using latest git (as of 12/08/2010) of libd
Alex Deucher wrote:
> Does reverting this part of the patch fix it?
>
> @@ -1055,10 +1055,10 @@ static void r600_texture_size(unsigned nfaces,
> unsigned blevel, unsigned nlevels
> }
> *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
> *mipmap_size = offset;
> - i
Andy Furniss wrote:
> No, it does make the nunbers bigger, though -
>
> radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
> 1048576 have 1409024)
Further (non exhaustive) testing shows it regresses some mesa demos as
well - lodbias,reflect & shadowtex -
mipmap bo too small (2
On Wed, Aug 18, 2010 at 7:45 AM, Andy Furniss wrote:
> Andy Furniss wrote:
>
>> No, it does make the nunbers bigger, though -
>>
>> radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
>> 1048576 have 1409024)
>
> Further (non exhaustive) testing shows it regresses some mesa demos as
Alex Deucher wrote:
> On Wed, Aug 18, 2010 at 7:45 AM, Andy Furniss wrote:
>> Andy Furniss wrote:
>>
>>> No, it does make the nunbers bigger, though -
>>>
>>> radeon :01:00.0: mipmap bo too small (512 512 4 0 0 1048576 ->
>>> 1048576 have 1409024)
>>
>> Further (non exhaustive) testing shows i
Asics that use an AGP to PCIE bridge don't have the AGP_STATUS
register so just use whatever mode the host side setup.
Signed-off-by: Alex Deucher
Cc: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_agp.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/gp
https://bugs.freedesktop.org/show_bug.cgi?id=29652
Summary: Git commit
Product: Mesa
Version: git
Platform: Other
OS/Version: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/R600
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #2 from Sven Arvidsson 2010-08-18 11:56:54 PDT ---
It seems to have regressed after the glsl2 merge it fails with "0:4(2):
preprocessor error: Invalid tokens after #" for both shaders.
/* Shader 2 source, checksum 0 */
#version 120
Last known good: 2.6.35
Failing kernel: 2.6.36-rc1
During boot kernel display this message:
[0.831906] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for plane,
expect flickering: entries required = 36, available = 28.
[0.895058] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for
https://bugs.freedesktop.org/show_bug.cgi?id=29652
Jon Severinsson changed:
What|Removed |Added
Summary|Git commit |Git commit e62e5b0 breaks
On Wed, 18 Aug 2010 20:46:37 +0200, Maciej Rutecki wrote:
> Last known good: 2.6.35
> Failing kernel: 2.6.36-rc1
>
> During boot kernel display this message:
> [0.831906] [drm:intel_calculate_wm] *ERROR* Insufficient FIFO for plane,
> expect flickering: entries required = 36, available = 28.
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #3 from Marek Ol??k 2010-08-18 12:37:15 PDT
---
Could you please file a new bug against the GLSL2 compiler (Mesa core, I guess)
to keep driver-specific and core bugs separate?
--
Configure bugmail: https://bugs.freedesktop.org/user
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #4 from Marek Ol??k 2010-08-18 12:39:08 PDT
---
Other than that, dynamic branching and loops should work with r300g to my
knowledge, I recall Tom adding the support for it just recently.
--
Configure bugmail: https://bugs.freedeskt
https://bugs.freedesktop.org/show_bug.cgi?id=28966
--- Comment #5 from Sven Arvidsson 2010-08-18 13:14:40 PDT ---
Filed as bug 29654
--
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
You are the assignee for the bug.
https://bugs.freedesktop.org/show_bug.cgi?id=28771
--- Comment #24 from Sven Arvidsson 2010-08-18 13:22:16 PDT ---
I compared how Intel (i965) compares when it comes to DRI2 and vsync, and as
far as I can tell they have the same problems (needs a special driver="dri2"
stansa in drirc, toggling vs
https://bugs.freedesktop.org/show_bug.cgi?id=29658
Summary: Crash when starting "spring rts" the system freeze:
/usr/lib/dri/r600_dri.so(radeon_bo_legacy_validate+0x4
83)
Product: Mesa
Version: unspecified
Platform:
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