Hi,
thank you. I found a presentation on AMD APUs that mentions throughtput
differences between different types of memory. This information helps me
a lot.
thanks again,
Jan
On Sat, 2015-02-21 at 10:24 -0500, Alex Deucher wrote:
> On Fri, Feb 20, 2015 at 7:21 PM, Jan Vesely wrote:
> > Hi,
> >
>
On Fri, Feb 20, 2015 at 7:21 PM, Jan Vesely wrote:
> Hi,
>
> thank you for exhaustive answer. I have few more
> questions/clarifications:
> is the DMA address used to access system pages further translated using
> IOMMU (if present), or are GPUs treated specially?
>
Yes, the address may be furthe
Hi,
thank you for exhaustive answer. I have few more
questions/clarifications:
is the DMA address used to access system pages further translated using
IOMMU (if present), or are GPUs treated specially?
I have only seen references to TLB flush, so I guess invalidating
individual entries is not sup
On Fri, Feb 20, 2015 at 12:35 PM, Jan Vesely wrote:
> Hello radeon devs,
>
> I have been trying to find out more about VM implementation on SI+ hw,
> but unfortunately I could not find much in the public documents[0].
>
> SI ISA manual suggests that there is a limited form of privileged mode
> on
Hello radeon devs,
I have been trying to find out more about VM implementation on SI+ hw,
but unfortunately I could not find much in the public documents[0].
SI ISA manual suggests that there is a limited form of privileged mode
on these chips, so I wondered if it could be used for VM management
