On Thu, Mar 21, 2024 at 09:47:18AM +0100, Sean Nyekjaer wrote:
> >> If HDMI is requiring a tolerance of 50 Hz, would it be better to do
> >> the check in the HDMI bridge driver?
> >
> > Judging from the code, it would be hard to do because the clock that
> > generates the pixel clock isn't exposed
Hi Raphael,
> On 20 Mar 2024, at 15.14, Raphael Gallais-Pou
> wrote:
>
>
> On 3/8/24 09:35, Sean Nyekjaer wrote:
>> Hi,
>
>
> Hi Sean,
>
>
> Sorry for not responding earlier.
NP :)
>
> I've also added Antonio Borneo, which is the author of the implementation of
> the
> mode_valid() hoo
Hi Maxime,
> On 20 Mar 2024, at 14.23, Maxime Ripard wrote:
>
> Hi Sean,
>
> On Fri, Mar 08, 2024 at 09:35:27AM +0100, Sean Nyekjaer wrote:
>> I’m using a stm32mp157 with a sn65dsi83 DSI2LVDS bridge. The LVDS
>> display is having a minimum clock of 25.2 MHz, typical of 27,2 MHz and
>> a max of
On 3/8/24 09:35, Sean Nyekjaer wrote:
> Hi,
Hi Sean,
Sorry for not responding earlier.
I've also added Antonio Borneo, which is the author of the implementation of the
mode_valid() hook.
> I’m using a stm32mp157 with a sn65dsi83 DSI2LVDS bridge.
> The LVDS display is having a minimum clock
Hi Sean,
On Fri, Mar 08, 2024 at 09:35:27AM +0100, Sean Nyekjaer wrote:
> I’m using a stm32mp157 with a sn65dsi83 DSI2LVDS bridge. The LVDS
> display is having a minimum clock of 25.2 MHz, typical of 27,2 MHz and
> a max of 30,5 MHz.
>
> I will fail the mode_valid check with MODE_CLOCK_RANGE. It
