On 21/12/2022 10:24, Tomi Valkeinen wrote:
> From: Tomi Valkeinen
>
> Hi,
>
> These add new pixel formats for Renesas V3U and V4H SoCs.
>
> As the display pipeline is split between DRM and V4L2 components, this
> series touches both subsystems. I'm sending all these together to
> simplify revie
Em Tue, 17 Jan 2023 15:38:25 +0200
Laurent Pinchart escreveu:
> Hi Tomi,
>
> (CC'ing Mauro and Hans)
>
> On Tue, Jan 10, 2023 at 04:25:37PM +0200, Tomi Valkeinen wrote:
> > On 26/12/2022 16:56, Laurent Pinchart wrote:
> > > Hi Tomi,
> > >
> > > (CC'ing Daniel and Dave)
> > >
> > > On Wed, D
Hi Tomi,
(CC'ing Mauro and Hans)
On Tue, Jan 10, 2023 at 04:25:37PM +0200, Tomi Valkeinen wrote:
> On 26/12/2022 16:56, Laurent Pinchart wrote:
> > Hi Tomi,
> >
> > (CC'ing Daniel and Dave)
> >
> > On Wed, Dec 21, 2022 at 11:24:41AM +0200, Tomi Valkeinen wrote:
> >> From: Tomi Valkeinen
> >>
>
On 26/12/2022 16:56, Laurent Pinchart wrote:
Hi Tomi,
(CC'ing Daniel and Dave)
On Wed, Dec 21, 2022 at 11:24:41AM +0200, Tomi Valkeinen wrote:
From: Tomi Valkeinen
Hi,
These add new pixel formats for Renesas V3U and V4H SoCs.
As the display pipeline is split between DRM and V4L2 components
Hi Tomi,
(CC'ing Daniel and Dave)
On Wed, Dec 21, 2022 at 11:24:41AM +0200, Tomi Valkeinen wrote:
> From: Tomi Valkeinen
>
> Hi,
>
> These add new pixel formats for Renesas V3U and V4H SoCs.
>
> As the display pipeline is split between DRM and V4L2 components, this
> series touches both subsy
