Hi Laurent
> > > + didsr = DIDSR_CODE;
> > > + for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
> > > + if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
> > > + didsr |= DIDSR_LCDS_LVDS0(i)
> > > + | DIDSR_PDCS_CLK(i, 0);
> > > + else
> > > +
Hi Morimoto-san,
On Tuesday, 27 November 2018 02:44:58 EET Kuninori Morimoto wrote:
> Hi Laurent
>
> Sorry for super late response.
> I got opinion from BSP team about this patch.
No worries. My reply is late too I'm afraid :-S
> > On selected SoCs, the DU can use the clock output by the LVDS e
Hi Laurent
Sorry for super late response.
I got opinion from BSP team about this patch.
> On selected SoCs, the DU can use the clock output by the LVDS encoder
> PLL as its input dot clock. This feature is optional, but on the D3 and
> E3 SoC it is often the only way to obtain a precise dot cloc
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> On selected SoCs, the DU can use the clock output by the LVDS encoder
> PLL as its input dot clock. This feature is optional, but on the D3 and
> E3 SoC it is often the only way to obtain a precise dot clock frequency,
> as th
Hi Laurent,
On Fri, Sep 14, 2018 at 12:10:37PM +0300, Laurent Pinchart wrote:
> On selected SoCs, the DU can use the clock output by the LVDS encoder
> PLL as its input dot clock. This feature is optional, but on the D3 and
> E3 SoC it is often the only way to obtain a precise dot clock frequency,
