Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On 4/11/24 23:46, Dmitry Baryshkov wrote: On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote: On 4/10/24 21:26, Dmitry Baryshkov wrote: On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote: On 4/6/24 05:23, Dmitry Baryshkov wrote: On Fri, Apr 05, 2024 at 10:41:32AM +0200, Kon

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On Fri, 12 Apr 2024 at 00:35, Konrad Dybcio wrote: > > > > On 4/10/24 21:26, Dmitry Baryshkov wrote: > > On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote: > >> > >> > >> On 4/6/24 05:23, Dmitry Baryshkov wrote: > >>> On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote: > >>>

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On 4/10/24 21:26, Dmitry Baryshkov wrote: On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote: On 4/6/24 05:23, Dmitry Baryshkov wrote: On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote: On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted t

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On Wed, Apr 10, 2024 at 01:42:33PM +0200, Konrad Dybcio wrote: > > > On 4/6/24 05:23, Dmitry Baryshkov wrote: > > On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote: > > > On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is > > > abstracted through SMEM, instead of bein

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On 4/6/24 05:23, Dmitry Baryshkov wrote: On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote: On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

Hi Konrad, kernel test robot noticed the following build errors: [auto build test ERROR on 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd] url: https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/soc-qcom-Move-some-socinfo-defines-to-the-header-expand-them/20240405-164231 base: 2b3d5988

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

Hi Konrad, kernel test robot noticed the following build errors: [auto build test ERROR on 2b3d5988ae2cb5cd945ddbc653f0a71706231fdd] url: https://github.com/intel-lab-lkp/linux/commits/Konrad-Dybcio/soc-qcom-Move-some-socinfo-defines-to-the-header-expand-them/20240405-164231 base: 2b3d5988

Re: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin

On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote: > On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is > abstracted through SMEM, instead of being directly available in a fuse. > > Add support for SMEM-based speed binning, which includes getting > "feature code" and "