Hi,
On 05/02/2025 07:53, Devarsh Thakkar wrote:
Hi Tomi
Thanks for pointing out, I probably missed this since the use-case still
worked since VP interrupts were still enabled and those were sufficient to
drive the display
but the VID underflow interrupts and VID specific bits were probably not
Hi Tomi
>> Thanks for pointing out, I probably missed this since the use-case still
>> worked since VP interrupts were still enabled and those were sufficient to
>> drive the display
>> but the VID underflow interrupts and VID specific bits were probably not
>> enabled at-all due to above miss, so
Hi,
On 28/01/2025 15:16, Devarsh Thakkar wrote:
Hi Aradhya,
On 18/01/25 14:57, Aradhya Bhatia wrote:
Hi Devarsh,
Thanks for the patches.
Thanks for the review.
On 31/12/24 14:34, Devarsh Thakkar wrote:
Enable display for AM62L DSS [1] which supports only a single display
pipeline using
Hi Aradhya,
On 18/01/25 14:57, Aradhya Bhatia wrote:
> Hi Devarsh,
>
> Thanks for the patches.
>
Thanks for the review.
> On 31/12/24 14:34, Devarsh Thakkar wrote:
>> Enable display for AM62L DSS [1] which supports only a single display
>> pipeline using a single overlay manager, single video po
Hi Devarsh,
Thanks for the patches.
On 31/12/24 14:34, Devarsh Thakkar wrote:
> Enable display for AM62L DSS [1] which supports only a single display
> pipeline using a single overlay manager, single video port and a single
> video lite pipeline which does not support scaling.
>
> The output of
Hi,
On 31/12/2024 11:04, Devarsh Thakkar wrote:
Enable display for AM62L DSS [1] which supports only a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary vi
