Hi,
On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on so
On 19/12/2022 12:00, Martin Blumenstingl wrote:
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione wrote:
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.
For SoCs not using
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing o