On Thu, 18 Jan 2024 23:02:31 +0100, Marek Vasut wrote:
> According to new configuration spreadsheet from Toshiba for TC9595,
> the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
> calculates those PLL input clock as reference clock divided by both
> pre-dividers. Add the extra limit
Am Donnerstag, dem 18.01.2024 um 23:02 +0100 schrieb Marek Vasut:
> According to new configuration spreadsheet from Toshiba for TC9595,
> the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
> calculates those PLL input clock as reference clock divided by both
> pre-dividers. Add the
