Re: [Intel-gfx] [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge

2012-08-17 Thread Lespiau, Damien
On Fri, Aug 17, 2012 at 4:00 PM, Keith Packard wrote: >> I guess this does not cover the case of pipe B using 3 lanes meaning >> pipe C can use 1? > > It didn't look like that was a supported mode from the docs. Ah yes, found it now "FDI B maximum port width is 4 lanes when FDI C is disabled, 2 l

Re: [Intel-gfx] [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge

2012-08-17 Thread Keith Packard
"Lespiau, Damien" writes: > On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard wrote: > > @@ -3728,7 +3728,8 @@ static inline bool intel_panel_use_ssc(struct > drm_i915_private *dev_priv) > */ > static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, >

Re: [Intel-gfx] [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge

2012-08-17 Thread Lespiau, Damien
On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard wrote: @@ -3728,7 +3728,8 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) */ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, unsigned int *pipe_bpp, -