Am 09.08.22 um 16:46 schrieb Daniel Vetter:
On Mon, Jul 04, 2022 at 03:48:03PM +0200, Christian König wrote:
Hi Daniel,
Am 25.06.22 um 00:02 schrieb Daniel Vetter:
On Thu, Jun 23, 2022 at 01:32:18PM +0200, Christian König wrote:
Am 23.06.22 um 13:27 schrieb Daniel Stone:
[SNIP]
If it's reall
On Mon, Feb 15, 2021 at 12:58 AM Christian König
wrote:
>
> Hi guys,
>
> we are currently working an Freesync and direct scan out from system
> memory on AMD APUs in A+A laptops.
>
> On problem we stumbled over is that our display hardware needs to scan
> out from uncached system memory and we cur
On Mon, Jul 04, 2022 at 03:48:03PM +0200, Christian König wrote:
> Hi Daniel,
>
> Am 25.06.22 um 00:02 schrieb Daniel Vetter:
> > On Thu, Jun 23, 2022 at 01:32:18PM +0200, Christian König wrote:
> > > Am 23.06.22 um 13:27 schrieb Daniel Stone:
> > > > [SNIP]
> > > > If it's really your belief that
Hi Daniel,
Am 25.06.22 um 00:02 schrieb Daniel Vetter:
On Thu, Jun 23, 2022 at 01:32:18PM +0200, Christian König wrote:
Am 23.06.22 um 13:27 schrieb Daniel Stone:
[SNIP]
If it's really your belief that dmabuf requires universal snooping, I
recommend you send the patch to update the documentati
Le lundi 27 juin 2022 à 16:06 +0200, Lucas Stach a écrit :
> Am Montag, dem 27.06.2022 um 09:54 -0400 schrieb Nicolas Dufresne:
> > Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> > > >
> > > > See for example on AMD/Intel hardware most of the engines can perfectly
> > > > deal with
Am Montag, dem 27.06.2022 um 09:54 -0400 schrieb Nicolas Dufresne:
> Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> > >
> > > See for example on AMD/Intel hardware most of the engines can perfectly
> > > deal with cache coherent memory accesses. Only the display engines can't.
> > >
Le jeudi 23 juin 2022 à 11:33 +0200, Lucas Stach a écrit :
> >
> > See for example on AMD/Intel hardware most of the engines can perfectly
> > deal with cache coherent memory accesses. Only the display engines can't.
> >
> > So on import time we can't even say if the access can be coherent and
Hi,
Le jeudi 23 juin 2022 à 10:58 +0200, Lucas Stach a écrit :
> > > In the DMA API keeping things mapped is also a valid use-case, but then
> > > you need to do explicit domain transfers via the dma_sync_* family,
> > > which DMA-buf has not inherited. Again those sync are no-ops on cache
> > > c
On Thu, Jun 23, 2022 at 01:32:18PM +0200, Christian König wrote:
> Am 23.06.22 um 13:27 schrieb Daniel Stone:
> > Hi Christian,
> >
> > On Thu, 23 Jun 2022 at 12:11, Christian König
> > wrote:
> > > > In fact DMA-buf sharing works fine on most of those SoCs because
> > > > everyone just assumes
Am Freitag, dem 24.06.2022 um 08:54 +0200 schrieb Christian König:
> Am 23.06.22 um 17:26 schrieb Lucas Stach:
> > Am Donnerstag, dem 23.06.2022 um 14:52 +0200 schrieb Christian König:
> > > Am 23.06.22 um 14:14 schrieb Lucas Stach:
> > > > Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Chris
Am 23.06.22 um 17:26 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 14:52 +0200 schrieb Christian König:
Am 23.06.22 um 14:14 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Christian König:
Am 23.06.22 um 13:29 schrieb Lucas Stach:
[SNIP]
I mean I even had som
Am Donnerstag, dem 23.06.2022 um 14:52 +0200 schrieb Christian König:
> Am 23.06.22 um 14:14 schrieb Lucas Stach:
> > Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Christian König:
> > > Am 23.06.22 um 13:29 schrieb Lucas Stach:
> > > [SNIP]
> > > I mean I even had somebody from ARM which to
Am 23.06.22 um 14:14 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Christian König:
Am 23.06.22 um 13:29 schrieb Lucas Stach:
[SNIP]
I mean I even had somebody from ARM which told me that this is not going
to work with our GPUs on a specific SoC. That there are ARM in
Am Donnerstag, dem 23.06.2022 um 13:54 +0200 schrieb Christian König:
> Am 23.06.22 um 13:29 schrieb Lucas Stach:
> > [SNIP]
> > > Well then the existing DMA-buf framework is not what you want to use for
> > > this.
> > >
> > Sorry, but this is just ignoring reality. You try to flag 8+ years of
>
Am 23.06.22 um 13:29 schrieb Lucas Stach:
[SNIP]
Well then the existing DMA-buf framework is not what you want to use for
this.
Sorry, but this is just ignoring reality. You try to flag 8+ years of
DMA-buf usage on non-coherent arches as "you shouldn't do this". At
this point there are probabl
Am 23.06.22 um 13:27 schrieb Daniel Stone:
Hi Christian,
On Thu, 23 Jun 2022 at 12:11, Christian König wrote:
In fact DMA-buf sharing works fine on most of those SoCs because
everyone just assumes that all the accelerators don't snoop, so the
memory shared via DMA-buf is mostly CPU uncached. I
Am Donnerstag, dem 23.06.2022 um 13:10 +0200 schrieb Christian König:
> Am 23.06.22 um 12:13 schrieb Lucas Stach:
> > [SNIP]
> > > > On most of the multimedia
> > > > targeted ARM SoCs being unable to snoop the cache is the norm, not an
> > > > exception.
> > > >
> > > > > See for example on AMD/I
Hi Christian,
On Thu, 23 Jun 2022 at 12:11, Christian König wrote:
> > In fact DMA-buf sharing works fine on most of those SoCs because
> > everyone just assumes that all the accelerators don't snoop, so the
> > memory shared via DMA-buf is mostly CPU uncached. It only falls apart
> > for uses li
Am 23.06.22 um 12:13 schrieb Lucas Stach:
[SNIP]
On most of the multimedia
targeted ARM SoCs being unable to snoop the cache is the norm, not an
exception.
See for example on AMD/Intel hardware most of the engines can perfectly
deal with cache coherent memory accesses. Only the display engines
Am Donnerstag, dem 23.06.2022 um 11:46 +0200 schrieb Christian König:
> Am 23.06.22 um 11:33 schrieb Lucas Stach:
> > [SNIP]
> > > > > > In the DMA API keeping things mapped is also a valid use-case, but
> > > > > > then
> > > > > > you need to do explicit domain transfers via the dma_sync_* famil
Am 23.06.22 um 11:33 schrieb Lucas Stach:
[SNIP]
In the DMA API keeping things mapped is also a valid use-case, but then
you need to do explicit domain transfers via the dma_sync_* family,
which DMA-buf has not inherited. Again those sync are no-ops on cache
coherent architectures, but do any ne
Am Donnerstag, dem 23.06.2022 um 11:09 +0200 schrieb Christian König:
> Am 23.06.22 um 10:58 schrieb Lucas Stach:
> > Am Donnerstag, dem 23.06.2022 um 10:14 +0200 schrieb Christian König:
> > > Am 23.06.22 um 10:04 schrieb Lucas Stach:
> > > > Am Donnerstag, dem 23.06.2022 um 09:26 +0200 schrieb Ch
Am 23.06.22 um 10:58 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 10:14 +0200 schrieb Christian König:
Am 23.06.22 um 10:04 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 09:26 +0200 schrieb Christian König:
Am 23.06.22 um 09:13 schrieb Pekka Paalanen:
On Thu, 23 Jun 2022 08:5
Am Donnerstag, dem 23.06.2022 um 10:14 +0200 schrieb Christian König:
> Am 23.06.22 um 10:04 schrieb Lucas Stach:
> > Am Donnerstag, dem 23.06.2022 um 09:26 +0200 schrieb Christian König:
> > > Am 23.06.22 um 09:13 schrieb Pekka Paalanen:
> > > > On Thu, 23 Jun 2022 08:59:41 +0200
> > > > Christian
Hi
Am 23.06.22 um 10:26 schrieb Christian König:
Am 23.06.22 um 10:13 schrieb Thomas Zimmermann:
Hi Christian
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbl
Am 23.06.22 um 10:13 schrieb Thomas Zimmermann:
Hi Christian
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled over is that our display hardware needs to
scan
Am 23.06.22 um 10:04 schrieb Lucas Stach:
Am Donnerstag, dem 23.06.2022 um 09:26 +0200 schrieb Christian König:
Am 23.06.22 um 09:13 schrieb Pekka Paalanen:
On Thu, 23 Jun 2022 08:59:41 +0200
Christian König wrote:
The exporter isn't doing anything wrong here. DMA-buf are supposed to be
CPU
Hi Christian
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled over is that our display hardware needs to scan
out from uncached system memory and we currently
Am Donnerstag, dem 23.06.2022 um 09:26 +0200 schrieb Christian König:
> Am 23.06.22 um 09:13 schrieb Pekka Paalanen:
> > On Thu, 23 Jun 2022 08:59:41 +0200
> > Christian König wrote:
> >
> > > The exporter isn't doing anything wrong here. DMA-buf are supposed to be
> > > CPU cached and can also b
Am 23.06.22 um 09:13 schrieb Pekka Paalanen:
On Thu, 23 Jun 2022 08:59:41 +0200
Christian König wrote:
The exporter isn't doing anything wrong here. DMA-buf are supposed to be
CPU cached and can also be cache hot.
Hi,
what is that statement based on?
On the design documentation of DMA-buf
On Thu, 23 Jun 2022 08:59:41 +0200
Christian König wrote:
> The exporter isn't doing anything wrong here. DMA-buf are supposed to be
> CPU cached and can also be cache hot.
Hi,
what is that statement based on?
Were the (mandatory for CPU access) cpu_access_begin/end functions &
ioctls not sup
Am 23.06.22 um 01:34 schrieb Daniel Stone:
Hi Nicolas,
On Wed, 22 Jun 2022 at 20:39, Nicolas Dufresne wrote:
Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
So I think if AMD also guarantees to drop clean cachelines just do the
same thing we do right now for intel integrated +
Hi Nicolas,
On Wed, 22 Jun 2022 at 20:39, Nicolas Dufresne wrote:
> Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
> > So I think if AMD also guarantees to drop clean cachelines just do the
> > same thing we do right now for intel integrated + discrete amd, but in
> > reserve. It
Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
> So I think if AMD also guarantees to drop clean cachelines just do the
> same thing we do right now for intel integrated + discrete amd, but in
> reserve. It's fragile, but it does work.
Sorry to disrupt, but if you pass V4L2 vmallo
Am 21.06.22 um 17:42 schrieb Nicolas Dufresne:
Hi Christian and Andy,
Le mardi 21 juin 2022 à 12:34 +0200, Christian König a écrit :
Hi Andy,
Am 21.06.22 um 12:17 schrieb Andy.Hsieh:
On 2/16/21 4:39 AM, Nicolas Dufresne wrote:
Le lundi 15 février 2021 à 09:58 +0100, Christian König
Hi Christian and Andy,
Le mardi 21 juin 2022 à 12:34 +0200, Christian König a écrit :
> Hi Andy,
>
> Am 21.06.22 um 12:17 schrieb Andy.Hsieh:
>
> > On 2/16/21 4:39 AM, Nicolas Dufresne wrote:
> > > Le lundi 15 février 2021 à 09:58 +0100, Christian König a écrit :
> > > > Hi guys,
> > > >
>
Hi Andy,
Am 21.06.22 um 12:17 schrieb Andy.Hsieh:
On 2/16/21 4:39 AM, Nicolas Dufresne wrote:
> Le lundi 15 février 2021 à 09:58 +0100, Christian König a écrit :
>> Hi guys,
>>
>> we are currently working an Freesync and direct scan out from system
>> memory on AMD APUs in A+A laptops.
>>
>> O
On Mon, Feb 15, 2021 at 09:58:08AM +0100, Christian König wrote:
> Hi guys,
>
> we are currently working an Freesync and direct scan out from system memory
> on AMD APUs in A+A laptops.
>
> On problem we stumbled over is that our display hardware needs to scan out
> from uncached system memory an
Le lundi 15 février 2021 à 09:58 +0100, Christian König a écrit :
> Hi guys,
>
> we are currently working an Freesync and direct scan out from system
> memory on AMD APUs in A+A laptops.
>
> On problem we stumbled over is that our display hardware needs to scan
> out from uncached system memory
Le lundi 15 février 2021 à 13:10 +0100, Christian König a écrit :
>
>
> Am 15.02.21 um 13:00 schrieb Thomas Zimmermann:
> > Hi
> >
> > Am 15.02.21 um 10:49 schrieb Thomas Zimmermann:
> > > Hi
> > >
> > > Am 15.02.21 um 09:58 schrieb Christian König:
> > > > Hi guys,
> > > >
> > > > we are curr
From: Christian König
> Sent: 15 February 2021 12:05
...
> Snooping the CPU caches introduces some extra latency, so what can
> happen is that the response to the PCIe read comes to late for the
> scanout. The result is an underflow and flickering whenever something is
> in the cache which needs to
Am 15.02.21 um 13:16 schrieb Lucas Stach:
[SNIP]
Userspace components can then of course tell the exporter what the
importer needs, but validation if that stuff is correct and doesn't
crash the system must happen in the kernel.
What exactly do you mean by "scanout requires non-coherent memory"?
Am Montag, dem 15.02.2021 um 13:04 +0100 schrieb Christian König:
> Am 15.02.21 um 12:53 schrieb Lucas Stach:
> > Am Montag, dem 15.02.2021 um 10:34 +0100 schrieb Christian König:
> > > Am 15.02.21 um 10:06 schrieb Simon Ser:
> > > > On Monday, February 15th, 2021 at 9:58 AM, Christian König
> > >
Am 15.02.21 um 13:00 schrieb Thomas Zimmermann:
Hi
Am 15.02.21 um 10:49 schrieb Thomas Zimmermann:
Hi
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled ove
Am 15.02.21 um 12:53 schrieb Lucas Stach:
Am Montag, dem 15.02.2021 um 10:34 +0100 schrieb Christian König:
Am 15.02.21 um 10:06 schrieb Simon Ser:
On Monday, February 15th, 2021 at 9:58 AM, Christian König
wrote:
we are currently working an Freesync and direct scan out from system
memory o
Hi
Am 15.02.21 um 10:49 schrieb Thomas Zimmermann:
Hi
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled over is that our display hardware needs to scan
out f
Am Montag, dem 15.02.2021 um 10:34 +0100 schrieb Christian König:
>
> Am 15.02.21 um 10:06 schrieb Simon Ser:
> > On Monday, February 15th, 2021 at 9:58 AM, Christian König
> > wrote:
> >
> > > we are currently working an Freesync and direct scan out from system
> > > memory on AMD APUs in A+A
Hi
Am 15.02.21 um 09:58 schrieb Christian König:
Hi guys,
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled over is that our display hardware needs to scan
out from uncached system memory and we currently don't hav
Am 15.02.21 um 10:06 schrieb Simon Ser:
On Monday, February 15th, 2021 at 9:58 AM, Christian König
wrote:
we are currently working an Freesync and direct scan out from system
memory on AMD APUs in A+A laptops.
On problem we stumbled over is that our display hardware needs to scan
out from
On Monday, February 15th, 2021 at 9:58 AM, Christian König
wrote:
> we are currently working an Freesync and direct scan out from system
> memory on AMD APUs in A+A laptops.
>
> On problem we stumbled over is that our display hardware needs to scan
> out from uncached system memory and we curren
50 matches
Mail list logo