Hi Hean Loong,
On Monday, 4 September 2017 09:09:11 EEST Ong, Hean Loong wrote:
> On Mon, 2017-08-28 at 13:06 +0800, Ong, Hean Loong wrote:
> > On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> >> On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> >>>
> >>> Hi Laurent,
Hi Laurent,
On Mon, 2017-08-28 at 13:06 +0800, Ong, Hean Loong wrote:
> Hi Laurent,
>
> On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> >
> > Hi Hean Loong,
> >
> > On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> > >
> > >
> > > Hi Laurent,
> > >
> > > I remov
Hi Laurent,
On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
>
> On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> >
> > Hi Laurent,
> >
> > I removed the examples for the HDMI in the draft below. The
> > connections
> > between the VIP and Display Po
Hello Hean Loon,
On Friday, 25 August 2017 04:21:17 EEST Ong, Hean Loong wrote:
> Hi Laurent,
>
> The encoder resides as a hardware logic as part of the FPGA fabric. The
> software driver has no direct access to the encoder. The VIP is created
> in such a way that the software i.e Linux Driver on
Hi Laurent,
The encoder resides as a hardware logic as part of the FPGA fabric. The
software driver has no direct access to the encoder. The VIP is created
in such a way that the software i.e Linux Driver only streams data
through the VIP. What happens beyond the VIP Frame buffer directly
boils do
Hi Hean Loong,
On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> Hi Laurent,
>
> I removed the examples for the HDMI in the draft below. The connections
> between the VIP and Display Port IP or any display connector are
> determined by HW logic. There are currently no SW defined
Hi Laurent,
I removed the examples for the HDMI in the draft below. The connections
between the VIP and Display Port IP or any display connector are
determined by HW logic. There are currently no SW defined encoders or
connectors that is connected to the AVALON-ST other than the Intel VIP
Frame Bu
Hi Hean Loong,
On Monday, 21 August 2017 04:40:09 EEST Ong, Hean Loong wrote:
> On Fri, 2017-08-18 at 16:11 +0300, Laurent Pinchart wrote:
> > On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> > >
> > > Hi Laurent,
> > > Thanks for the comments, I drafted a copy of the DT bindings based
> >
Hi Laurent Thanks. my replies are below
On Fri, 2017-08-18 at 16:11 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
>
> (CC'ing dri-devel again as I noticed it wasn't CC'ed anymore)
>
> On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> >
> > Hi Laurent,
> > Thanks for the comments, I draf
Hi Hean Loong,
(CC'ing dri-devel again as I noticed it wasn't CC'ed anymore)
On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> Hi Laurent,
> Thanks for the comments, I drafted a copy of the DT bindings based on
> your recommendations and inputs. I inserted the changes below the
> previous c
On Thu, 2017-08-17 at 10:22 -0500, Rob Herring wrote:
> On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> >
> > From: Ong Hean Loong
> "dt-bindings: display: ..." for the subject. With that,
>
> Acked-by: Rob Herring
>
> >
> >
> > Device tree binding for Intel FPGA Video and
On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> From: Ong Hean Loong
"dt-bindings: display: ..." for the subject. With that,
Acked-by: Rob Herring
>
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the A
From: Ong Hean Loong
Device tree binding for Intel FPGA Video and Image
Processing Suite. The binding involved would be generated
from the Altera (Intel) Qsys system. The bindings would
set the max width, max height, buts per pixel and memory
port width. The device tree binding only supports the
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