Thanks Neil.
On Thu, 2017-05-04 at 09:55 +0200, Neil Armstrong wrote:
> On 04/25/2017 04:06 AM, hean.loong@intel.com wrote:
> >
> > From: "Ong, Hean Loong"
> >
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would be generated
> > from the
On 04/25/2017 04:06 AM, hean.loong@intel.com wrote:
> From: "Ong, Hean Loong"
>
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per
On Fri, 2017-04-28 at 13:32 -0500, Rob Herring wrote:
> On Tue, Apr 25, 2017 at 10:06:44AM +0800, hean.loong@intel.com
> wrote:
> >
> > From: "Ong, Hean Loong"
> >
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would be generated
> > from th
On Tue, Apr 25, 2017 at 10:06:44AM +0800, hean.loong@intel.com wrote:
> From: "Ong, Hean Loong"
>
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max
From: "Ong, Hean Loong"
Device tree binding for Intel FPGA Video and Image
Processing Suite. The binding involved would be generated
from the Altera (Intel) Qsys system. The bindings would
set the max width, max height, buts per pixel and memory
port width. The device tree binding only supports t
