On 28/03/17 08:45, Jyri Sarha wrote:
> On 03/24/17 11:40, Tomi Valkeinen wrote:
>> DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
>> says that FPDLink is sensitive to jitter on the vout clock, and that low
>> PLL M and N values result in more jitter than high M and N values.
On 03/24/17 11:40, Tomi Valkeinen wrote:
> DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
> says that FPDLink is sensitive to jitter on the vout clock, and that low
> PLL M and N values result in more jitter than high M and N values.
>
> This patch implements a workaround f
DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
says that FPDLink is sensitive to jitter on the vout clock, and that low
PLL M and N values result in more jitter than high M and N values.
This patch implements a workaround for the problem by changing the PLL
setup to search
