Hi Hyun,
Thank you for the patch.
On Sat, Jul 07, 2018 at 07:05:36PM -0700, Hyun Kwon wrote:
> Xilinx ZynqMP has a hardened display pipeline. The pipeline can
> be logically partitioned into 2 parts: display controller and
> DisplayPort encoder / transmitter. This driver handles the display
> con
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
Ac
