Hi Hyun
Thank you for the patch.
On Sat, Jul 07, 2018 at 07:05:34PM -0700, Hyun Kwon wrote:
> Xilinx has various platforms for display, where users can create
> using multiple IPs in the programmable FPGA fabric, or where
> some hardened pipeline is available on the chip. Furthermore,
> hardened
Xilinx has various platforms for display, where users can create
using multiple IPs in the programmable FPGA fabric, or where
some hardened pipeline is available on the chip. Furthermore,
hardened pipeline can also interact with soft logics in FPGA.
The Xilinx DRM KMS module is to integrate multip
