On Wed, Apr 23, 2025 at 10:50 AM Jun Nie wrote:
> Pengyu Luo 于2025年4月19日周六 02:34写道：
> >
> > On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie wrote:
> > > 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> > > And 4 DSC are preferred for power optimal in this case due to width
> >
Pengyu Luo 于2025年4月19日周六 02:34写道：
>
> On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie wrote:
> > 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> > And 4 DSC are preferred for power optimal in this case due to width
> > limitation of SSPP and MDP clock rate constrain. This patch
On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie wrote:
> 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> And 4 DSC are preferred for power optimal in this case due to width
> limitation of SSPP and MDP clock rate constrain. This patch set
> extends number of pipes to 4 and revis
2 or more SSPPs and dual-DSI interface are need for super wide panel.
And 4 DSC are preferred for power optimal in this case due to width
limitation of SSPP and MDP clock rate constrain. This patch set
extends number of pipes to 4 and revise related mixer blending logic
to support quad pipe. All th
