Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(
On 5/11/2022 12:11 PM, Ceraolo Spurio, Daniele wrote:
On 3/18/2022 4:39 PM, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zer
On 3/18/2022 4:39 PM, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compa
Hi Michal,
[...]
> > +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> > +{
> > + int ret;
> > +
> > + if (!gt_is_root(gt)) {
> > + struct intel_uncore_mmio_debug *mmio_debug;
> > + struct intel_uncore *uncore;
> > +
> > + uncore = kza
On 19.03.2022 00:39, Andi Shyti wrote:
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable s
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each
