On Thu, Feb 11, 2016 at 07:19:45PM +0100, David Herrmann wrote:
> Hi
>
> On Thu, Feb 11, 2016 at 7:08 PM, Ville Syrjälä
> wrote:
> > On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote:
> >>
> >> Thanks for reviewing, David. Please take a look in my comments in-line.
> >>
> >>
> >> O
On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote:
>
> Thanks for reviewing, David. Please take a look in my comments in-line.
>
>
> On 02/09/2016 07:26 AM, David Herrmann wrote:
> >
> > On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
> > wrote:
> >> From: Daniel Vetter
> >> +
>
Hi
On Thu, Feb 11, 2016 at 7:08 PM, Ville Syrjälä
wrote:
> On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote:
>>
>> Thanks for reviewing, David. Please take a look in my comments in-line.
>>
>>
>> On 02/09/2016 07:26 AM, David Herrmann wrote:
>> >
>> > On Tue, Dec 22, 2015 at 10:36
Hi
On Thu, Feb 11, 2016 at 6:54 PM, Tiago Vignatti
wrote:
> On 02/09/2016 07:26 AM, David Herrmann wrote:
>>> +
>>> + switch (cmd) {
>>> + case DMA_BUF_IOCTL_SYNC:
>>> + if (copy_from_user(&sync, (void __user *) arg,
>>> sizeof(sync)))
>>> + return
Thanks for reviewing, David. Please take a look in my comments in-line.
On 02/09/2016 07:26 AM, David Herrmann wrote:
>
> On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
> wrote:
>> From: Daniel Vetter
>>
>> The userspace might need some sort of cache coherency management e.g. when
>> CPU
>>
On Thu, Feb 11, 2016 at 12:54 PM, Tiago Vignatti
wrote:
>
> Thanks for reviewing, David. Please take a look in my comments in-line.
>
>
> On 02/09/2016 07:26 AM, David Herrmann wrote:
>>
>>
>> On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
>> wrote:
>>>
>>> From: Daniel Vetter
>>>
>>> The user
On Tue, Feb 09, 2016 at 11:20:20AM +0100, Daniel Vetter wrote:
> On Tue, Feb 09, 2016 at 10:26:25AM +0100, David Herrmann wrote:
> > Hi
> >
> > On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
> > wrote:
> > > From: Daniel Vetter
> > >
> > > The userspace might need some sort of cache coherency
On Tue, Feb 09, 2016 at 10:26:25AM +0100, David Herrmann wrote:
> Hi
>
> On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
> wrote:
> > From: Daniel Vetter
> >
> > The userspace might need some sort of cache coherency management e.g. when
> > CPU
> > and GPU domains are being accessed through dm
Hi
On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
wrote:
> From: Daniel Vetter
>
> The userspace might need some sort of cache coherency management e.g. when CPU
> and GPU domains are being accessed through dma-buf at the same time. To
> circumvent this problem there are begin/end coherency ma
From: Daniel Vetter
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc
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