Re: [PATCH v6 1/3] drm/bridge: ti-sn65dsi86: Reject modes with too large blanking

2022-09-01 Thread Robert Foss
On Wed, 31 Aug 2022 at 10:27, Tomi Valkeinen wrote: > > From: Tomi Valkeinen > > The front and back porch registers are 8 bits, and pulse width registers > are 15 bits, so reject any modes with larger periods. > > Signed-off-by: Tomi Valkeinen > --- > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23

[PATCH v6 1/3] drm/bridge: ti-sn65dsi86: Reject modes with too large blanking

2022-08-31 Thread Tomi Valkeinen
From: Tomi Valkeinen The front and back porch registers are 8 bits, and pulse width registers are 15 bits, so reject any modes with larger periods. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 23 +++ 1 file changed, 23 insertions(+) diff --git