On Sat, Sep 14, 2024 at 10:12:29PM GMT, Cristian Ciocaltea wrote:
> Hi Maxime,
>
> On 9/9/24 6:13 PM, Maxime Ripard wrote:
> > Hi,
> >
> > On Fri, Sep 06, 2024 at 04:17:40AM GMT, Cristian Ciocaltea wrote:
> >> +static enum drm_connector_status
> >> +dw_hdmi_qp_bridge_detect(struct drm_bridge *bri
Hi Maxime,
On 9/9/24 6:13 PM, Maxime Ripard wrote:
> Hi,
>
> On Fri, Sep 06, 2024 at 04:17:40AM GMT, Cristian Ciocaltea wrote:
>> +static enum drm_connector_status
>> +dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge)
>> +{
>> +struct dw_hdmi_qp *hdmi = bridge->driver_private;
>> +enum
Hi,
On Fri, Sep 06, 2024 at 04:17:40AM GMT, Cristian Ciocaltea wrote:
> +static enum drm_connector_status
> +dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge)
> +{
> + struct dw_hdmi_qp *hdmi = bridge->driver_private;
> + enum drm_connector_status status;
> +
> + status = hdmi->phy.o
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller IP
supports the following features, among others:
* Fixed Rate Link (FRL)
* Display Stream Compression (DSC)
* 4K@120Hz and 8K@60Hz video modes
* Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka
Cinema VRR
* Fas
