This series implements preemption for A7XX targets, which allows the GPU to
switch to an higher priority ring when work is pushed to it, reducing latency
for high priority submissions.
This series enables L1 preemption with skip_save_restore which requires
the following userspace patches to functi
This series introduces support for big and super pages in V3D. The V3D MMU has
support for 64KB and 1MB pages, called big pages and super pages, which are
currently not used. Therefore, this patchset has the intention to enable big and
super pages in V3D. The advantage of enabling big and super pag
On Mon, Jul 17, 2023 at 10:14 PM AngeloGioacchino Del Regno
wrote:
>
> Changes in v6:
> - Added some previously missing error checking (patch [01/11])
> - Added error checks for devm_drm_bridge_add()
> - Made sure that cable_plugged_in is set to false if HPD assertion
>polling fails (timeou
Changes in v6:
- Added some previously missing error checking (patch [01/11])
- Added error checks for devm_drm_bridge_add()
- Made sure that cable_plugged_in is set to false if HPD assertion
polling fails (timeout)
- Support panel as module (tested with panel-edp on MT8195 Tomato)
- Rebase
Il 12/06/23 11:01, AngeloGioacchino Del Regno ha scritto:
Changes in v6:
- Fixed smatch warning in patch 11/11, ref.:
https://lore.kernel.org/all/202306101458.lrxhee0z-...@intel.com/
This series is fully ready. CK, can we get this one and the mtk-dp series [1]
in -next for this cycle ple
Changes in v6:
- Fixed smatch warning in patch 11/11, ref.:
https://lore.kernel.org/all/202306101458.lrxhee0z-...@intel.com/
Changes in v5:
- Removed incorrect comment on default LUT size and bits
- Removed useless check for num_lut_banks
- Added comment about CMDQ implementation on patch 5
Krzysztof asked me to merge all pending MDSS/MDP5/DPU patches to a
single series to ease review and to let one to see the whole picture.
This combines three series: MDP5 schema conversion, mdss/mdp renaming
and addition of the "core" clock to the MDSS device node.
Changes since v5:
- Merged in th
On Wed, 07 Dec 2022 03:22:20 +0200, Dmitry Baryshkov wrote:
> This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
>
> Change since v5:
> - Added defines to be used for the MDP_PERIPH_TOP0 blackhole
>
> Change since v4:
> - Fixed commit messages for the first two patches (Krz
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Change since v5:
- Added defines to be used for the MDP_PERIPH_TOP0 blackhole
Change since v4:
- Fixed commit messages for the first two patches (Krzysztof)
- Dropped clock-names requirement patch
- Removed clock-names from q
On Thu, 31 Mar 2022 at 17:20, Marek Vasut wrote:
>
> The TC358767/TC358867/TC9595 are all capable of operating in multiple
> modes, DPI-to-(e)DP, DSI-to-(e)DP, DSI-to-DPI. Clean up the driver,
> switch to atomic ops, and add support for the DSI-to-DPI mode in
> addition to already supported DPI-to
On Thu, 31 Mar 2022 at 17:05, Marek Vasut wrote:
>
> This series fixes multiple problems with the ICN6211 driver and adds
> support for configuration of the chip via I2C bus.
>
> First, in the current state, the ICN6211 driver hard-codes DPI timing
> and clock settings specific to some unknown pan
The TC358767/TC358867/TC9595 are all capable of operating in multiple
modes, DPI-to-(e)DP, DSI-to-(e)DP, DSI-to-DPI. Clean up the driver,
switch to atomic ops, and add support for the DSI-to-DPI mode in
addition to already supported DPI-to-(e)DP mode.
Cc: Jonas Karlman
Cc: Laurent Pinchart
Cc: M
This series fixes multiple problems with the ICN6211 driver and adds
support for configuration of the chip via I2C bus.
First, in the current state, the ICN6211 driver hard-codes DPI timing
and clock settings specific to some unknown panel. The settings provided
by panel driver are ignored. Using
Hi,
the first patch concludes the first stage of refactoring which
makes the use of intel_gt on the different subsystem. It's taken
from Matt's series and it has alread been reviewed. The patch has
just been replaced before any multitile patches and I think it
can be already pushed.
Patch 2-10 ar
On 8/22/21 6:19 PM, Jim Cromie wrote:
> This patchset does 3 main things.
>
> Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category
> control of pr_debugs, and to create their sysfs entries.
>
> Uses it in amdgpu, i915 to control existing pr_debugs according to
> their ad-hoc categ
This patchset does 3 main things.
Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category
control of pr_debugs, and to create their sysfs entries.
Uses it in amdgpu, i915 to control existing pr_debugs according to
their ad-hoc categorizations.
Plugs dyndbg into drm-debug framework, in
On Wed, 2021-07-14 at 10:59 +0200, Frank Wunderlich wrote:
> Hi,
>
> sorry this (or the 2 depency-series) cause a NULL Pointer deref in
> iommu_group_remove_device on mt7623/bpi-r2
Hi Frank,
Thanks for your report. mt7623 use mtk_iommu_v1.c.
I will try to reproduce this locally.
>
> i wonder
On Wed, 2021-07-14 at 10:56 +0200, Dafna Hirschfeld wrote:
> Hi
>
> Thanks for the patchset.
>
> I tested it on mt8173 (elm) with chromeos userspace.
> Before that patchset, the test:
>
> tast -verbose run -build=false 10.42.0.175 video.DecodeAccel.h264
>
> sometimes passed and sometimes failed
> Gesendet: Mittwoch, 14. Juli 2021 um 13:18 Uhr
> Von: "Yong Wu"
> Hi Frank,
>
> Thanks for your report. mt7623 use mtk_iommu_v1.c.
>
> I will try to reproduce this locally.
Hi,
as far as i have debugged it dev->iommu_group is NULL, so it crashes on first
access (dev_info)
drivers/iommu/iommu
Hi,
sorry this (or the 2 depency-series) cause a NULL Pointer deref in
iommu_group_remove_device on mt7623/bpi-r2
i wonder why on bootup a cleanup is run, but have no hint about this.
since "dts: mtk-mdp: remove mediatek, vpu property from primary MDP device" all
is good, i guess problem comes
Hi
Thanks for the patchset.
I tested it on mt8173 (elm) with chromeos userspace.
Before that patchset, the test:
tast -verbose run -build=false 10.42.0.175 video.DecodeAccel.h264
sometimes passed and sometimes failed with 'context deadline exceeded'.
With this patchset it seems that the test a
MediaTek IOMMU block diagram always like below:
M4U
|
smi-common
|
-
| | ...
| |
larb1 larb2
| |
vdec venc
All the consumer connect with smi-larb, then connect with smi-common.
When the consumer works, it should
This patch set adds a new drm driver for HiSilicon Kirin hi6220 SoC.
Current testing and support board is Hikey board which is one of Linaro
96boards. It is an arm64 open source board. For more information about
this board, please access https://www.96boards.org.
Hardware Detail
---
Let me fill in the subject line so people know what it is about :-)
Hans
On 06/16/15 08:22, Hans Verkuil wrote:
> On 05/04/2015 07:32 PM, Kamil Debski wrote:
>> Hi,
>>
>> The sixth version of this patchset addresses recent comments on the mailing
>> list. Please see the changelog below fo
On 05/04/2015 07:32 PM, Kamil Debski wrote:
> Hi,
>
> The sixth version of this patchset addresses recent comments on the mailing
> list. Please see the changelog below for details.
Just in case people are wondering what happened to this: about a month ago I
took over from Kamil and I am working
nux-
> input at vger.kernel.org; linux-samsung-soc at vger.kernel.org;
> lars at opdenkamp.eu
> Subject: [PATCH v6 00/11]
>
> Hi,
>
> The sixth version of this patchset addresses recent comments on the
> mailing list. Please see the changelog below for details.
Hi,
The sixth version of this patchset addresses recent comments on the mailing
list. Please see the changelog below for details.
Best wishes,
Kamil Debski
Changes since v5
- drop struct cec_timeval in favour of a __u64 that keeps the timestamp in ns
- remove userspace documenta
Hello,
This patch series adds support for the Atmel HLCDC block (HLCD Controller)
available on some Atmel SoCs (i.e. the sama5d3 family).
The HLCDC actually provides a Display Controller and a PWM device, hence I
decided to declare an MFD device exposing 2 subdevices: a display
controller and a P
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