On 22/10/24 11:55, Devarsh Thakkar wrote:
> Hi Aradhya,
>
> Thanks for the patch.
>
> On 20/10/24 01:24, Aradhya Bhatia wrote:
>> From: Aradhya Bhatia
>
> [...]
>
>> +/*
>> + * Now that the DSI Link and DSI Phy are initialized,
>> + * wait for the CLK and Data Lanes to be ready.
Hi Aradhya,
Thanks for the patch.
On 20/10/24 01:24, Aradhya Bhatia wrote:
> From: Aradhya Bhatia
[...]
> + /*
> + * Now that the DSI Link and DSI Phy are initialized,
> + * wait for the CLK and Data Lanes to be ready.
> + */
> + tmp = CLK_LANE_RDY;
> + for (int i =
From: Aradhya Bhatia
Once the DSI Link and DSI Phy are initialized, the code needs to wait
for Clk and Data Lanes to be ready, before continuing configuration.
This is in accordance with the DSI Start-up procedure, found in the
Technical Reference Manual of Texas Instrument's J721E SoC[0] which
h
