On 03/05/2025 00:42, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote:
>> On SM8750 the setting rate of pixel and byte clocks, while the parent
>> DSI PHY PLL, fails with:
>>
>> disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
>>
>> DSI
On Wed, Apr 30, 2025 at 03:00:36PM +0200, Krzysztof Kozlowski wrote:
> On SM8750 the setting rate of pixel and byte clocks, while the parent
> DSI PHY PLL, fails with:
>
> disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
>
> DSI PHY PLL has to be unprepared and its "PLL Power Do
On SM8750 the setting rate of pixel and byte clocks, while the parent
DSI PHY PLL, fails with:
disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
CMN_CTRL_0 asserted.
Mark these clocks with CLK_OPS_PARENT_ENABLE to
