Hi Iago,
On 9/4/24 05:24, Iago Toral wrote:
Hi Maira,
El jue, 29-08-2024 a las 10:05 -0300, Maíra Canal escribió:
We must first flush the MMU cache and then, flush the TLB, not the
other
way around. Currently, we can see a race condition between the MMU
cache
and the TLB when running multiple
Hi Maira,
El jue, 29-08-2024 a las 10:05 -0300, Maíra Canal escribió:
> We must first flush the MMU cache and then, flush the TLB, not the
> other
> way around. Currently, we can see a race condition between the MMU
> cache
> and the TLB when running multiple rendering processes at the same
> time
We must first flush the MMU cache and then, flush the TLB, not the other
way around. Currently, we can see a race condition between the MMU cache
and the TLB when running multiple rendering processes at the same time.
This is evidenced by MMU errors triggered by the IRQ.
Fix the MMU flush order by
