[PATCH v4 4/8] drm/exynos: dsi: rename pll_clk to sclk_clk

2015-04-07 Thread Inki Dae
On 2015년 04월 07일 20:57, Hyungwon Hwang wrote: > This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk > is actually not the pll input clock for dsi. The pll input clock comes > from the board's oscillator directly. > > Signed-off-by: Hyungwon Hwang > --- > Changes for v3:

[PATCH v4 4/8] drm/exynos: dsi: rename pll_clk to sclk_clk

2015-04-07 Thread Hyungwon Hwang
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. Signed-off-by: Hyungwon Hwang --- Changes for v3: - Newly added Changes for v4: - None .../devicetree/bindings/vid