Hello,
Am 13.03.25 um 20:04 schrieb Maíra Canal:
+Cc Stefan
Hi Krzysztof,
On 13/03/25 12:03, Krzysztof Kozlowski wrote:
On 13/03/2025 15:43, Maíra Canal wrote:
In order to enforce per-SoC register rules, add per-compatible
restrictions. V3D 3.3 (represented by brcm,7268-v3d) has a cache
cont
On 3/15/2025 5:17 AM, Maíra Canal wrote:
Hi Stefan,
On 15/03/25 06:52, Stefan Wahren wrote:
Hello,
Am 13.03.25 um 20:04 schrieb Maíra Canal:
+Cc Stefan
Hi Krzysztof,
On 13/03/25 12:03, Krzysztof Kozlowski wrote:
On 13/03/2025 15:43, Maíra Canal wrote:
In order to enforce per-SoC regist
Hi Stefan,
On 15/03/25 06:52, Stefan Wahren wrote:
Hello,
Am 13.03.25 um 20:04 schrieb Maíra Canal:
+Cc Stefan
Hi Krzysztof,
On 13/03/25 12:03, Krzysztof Kozlowski wrote:
On 13/03/2025 15:43, Maíra Canal wrote:
In order to enforce per-SoC register rules, add per-compatible
restrictions. V3
+Cc Stefan
Hi Krzysztof,
On 13/03/25 12:03, Krzysztof Kozlowski wrote:
On 13/03/2025 15:43, Maíra Canal wrote:
In order to enforce per-SoC register rules, add per-compatible
restrictions. V3D 3.3 (represented by brcm,7268-v3d) has a cache
controller (GCA), which is not present in other V3D gen
On 13/03/2025 15:43, Maíra Canal wrote:
> In order to enforce per-SoC register rules, add per-compatible
> restrictions. V3D 3.3 (represented by brcm,7268-v3d) has a cache
> controller (GCA), which is not present in other V3D generations.
> Declaring these differences helps ensure the DTB accuratel
In order to enforce per-SoC register rules, add per-compatible
restrictions. V3D 3.3 (represented by brcm,7268-v3d) has a cache
controller (GCA), which is not present in other V3D generations.
Declaring these differences helps ensure the DTB accurately reflect
the hardware design.
While not ideal,
