Hi,
On 04/07/2025 12:48, Jayesh Choudhary wrote:
> TIDSS hardware by itself does not have variable max_pclk for each VP.
> The maximum pixel clock is determined by the limiting factor between
> the functional clock and the PLL (parent to the VP/pixel clock).
I'm sorry, what does that mean? "limit
TIDSS hardware by itself does not have variable max_pclk for each VP.
The maximum pixel clock is determined by the limiting factor between
the functional clock and the PLL (parent to the VP/pixel clock).
The limitation that has been modeled till now comes from the clock
(PLL can only be programmed
