Rob Herring ; Daniel
> Vetter ; Laurent Pinchart
>
> Subject: Re: [PATCH v3 2/8] drm: xlnx: Xilinx DRM KMS driver
>
> On Mon, Jan 15, 2018 at 05:57:05PM -0800, Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple IPs in
On Wed, Jan 17, 2018 at 09:20:28AM +0100, Daniel Vetter wrote:
> On Mon, Jan 15, 2018 at 05:57:05PM -0800, Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple IPs in the programmable FPGA fabric, or where
> > some hardened piepline is available o
On Mon, Jan 15, 2018 at 05:57:05PM -0800, Hyun Kwon wrote:
> Xilinx has various platforms for display, where users can create
> using multiple IPs in the programmable FPGA fabric, or where
> some hardened piepline is available on the chip. Furthermore,
> hardened pipeline can also interact with sof
On Mon, Jan 15, 2018 at 05:57:05PM -0800, Hyun Kwon wrote:
> +static struct drm_driver xlnx_drm_driver = {
> + .driver_features= DRIVER_MODESET | DRIVER_GEM |
> + DRIVER_ATOMIC | DRIVER_PRIME,
> + .lastclose =
Xilinx has various platforms for display, where users can create
using multiple IPs in the programmable FPGA fabric, or where
some hardened piepline is available on the chip. Furthermore,
hardened pipeline can also interact with soft logics in FPGA.
The Xilinx DRM KMS is to integrate multiple subd
