On Wed, 2022-09-21 at 08:28 +0200, Krzysztof Kozlowski wrote:
> On 21/09/2022 06:16, Jason-JH Lin wrote:
> > Hi Krzysztof,
> >
> > Thanks for the reviews.
> >
> > On Tue, 2022-09-20 at 17:25 +0200, Krzysztof Kozlowski wrote:
> > > On 20/09/2022 16:01, Jason-JH.Lin wrote:
> > > > For previous Medi
On 21/09/2022 06:16, Jason-JH Lin wrote:
> Hi Krzysztof,
>
> Thanks for the reviews.
>
> On Tue, 2022-09-20 at 17:25 +0200, Krzysztof Kozlowski wrote:
>> On 20/09/2022 16:01, Jason-JH.Lin wrote:
>>> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
>>> pipelines binding to 1 mmsy
Hi Krzysztof,
Thanks for the reviews.
On Tue, 2022-09-20 at 17:25 +0200, Krzysztof Kozlowski wrote:
> On 20/09/2022 16:01, Jason-JH.Lin wrote:
> > For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> > pipelines binding to 1 mmsys with the same power domain, the same
> > clock dri
On 20/09/2022 16:01, Jason-JH.Lin wrote:
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
>
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drive
