On Sat, 12 Jul 2014 14:37:16 -0400
Rob Clark wrote:
> On Sat, Jul 12, 2014 at 2:16 PM, Boris BREZILLON
> wrote:
> > Hello,
> >
> > On Mon, 7 Jul 2014 18:42:58 +0200
> > Boris BREZILLON wrote:
> >
> >
> >> +int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
> >> +{
> >> + struct
Hello,
On Mon, 7 Jul 2014 18:42:58 +0200
Boris BREZILLON wrote:
> +int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
> +{
> + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
> + unsigned long flags;
> + int i;
> +
> + spin_lock_irqsave(&dma->lock, flags);
On Sat, Jul 12, 2014 at 2:16 PM, Boris BREZILLON
wrote:
> Hello,
>
> On Mon, 7 Jul 2014 18:42:58 +0200
> Boris BREZILLON wrote:
>
>
>> +int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
>> +{
>> + struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
>> + unsigned long fl
On Wed, Jul 09, 2014 at 09:14:24AM +0200, Boris BREZILLON wrote:
> Hi Matt,
>
> On Tue, 8 Jul 2014 16:51:24 -0700
> Matt Roper wrote:
>
> > Hi Boris.
> >
> > I haven't really looked at any of your driver in depth, but from a quick
> > glance it looks like you're registering a cursor drm_plane (
On Mon, 7 Jul 2014 23:45:54 -0400
Rob Clark wrote:
> On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
> wrote:
> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> > at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> > controller device.
> >
> > This
Hi Matt,
On Tue, 8 Jul 2014 16:51:24 -0700
Matt Roper wrote:
> Hi Boris.
>
> I haven't really looked at any of your driver in depth, but from a quick
> glance it looks like you're registering a cursor drm_plane (i.e., making
> use of the new universal plane infrastructure), but you're also
> pr
On Wed, Jul 9, 2014 at 4:18 AM, Boris BREZILLON
wrote:
> On Mon, 7 Jul 2014 23:45:54 -0400
> Rob Clark wrote:
>
>> On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
>> wrote:
>> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
>> > at91sam9n12, at91sam9x5 family or sama5d
On Tue, 8 Jul 2014 11:41:32 -0400
Rob Clark wrote:
> On Tue, Jul 8, 2014 at 10:37 AM, Boris BREZILLON
> wrote:
> > On Tue, 8 Jul 2014 08:49:41 -0400
> > Rob Clark wrote:
> >
> >> On Tue, Jul 8, 2014 at 3:23 AM, Boris BREZILLON
> >> wrote:
> >> > Hello Rob,
> >> >
> >> > On Mon, 7 Jul 2014 23:4
On Tue, Jul 08, 2014 at 07:08:20PM +0200, Boris BREZILLON wrote:
> On Tue, 8 Jul 2014 11:41:32 -0400
> Rob Clark wrote:
>
> > On Tue, Jul 8, 2014 at 10:37 AM, Boris BREZILLON
> > wrote:
> > > On Tue, 8 Jul 2014 08:49:41 -0400
> > > Rob Clark wrote:
> > >
> > >> On Tue, Jul 8, 2014 at 3:23 AM, B
On Tue, 8 Jul 2014 08:49:41 -0400
Rob Clark wrote:
> On Tue, Jul 8, 2014 at 3:23 AM, Boris BREZILLON
> wrote:
> > Hello Rob,
> >
> > On Mon, 7 Jul 2014 23:45:54 -0400
> > Rob Clark wrote:
> >
> >> On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
> >> wrote:
> >> > The Atmel HLCDC (HLCD Control
On Tue, Jul 8, 2014 at 10:37 AM, Boris BREZILLON
wrote:
> On Tue, 8 Jul 2014 08:49:41 -0400
> Rob Clark wrote:
>
>> On Tue, Jul 8, 2014 at 3:23 AM, Boris BREZILLON
>> wrote:
>> > Hello Rob,
>> >
>> > On Mon, 7 Jul 2014 23:45:54 -0400
>> > Rob Clark wrote:
>> >
>> >> On Mon, Jul 7, 2014 at 12:42
Hello Rob,
On Mon, 7 Jul 2014 23:45:54 -0400
Rob Clark wrote:
> On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
> wrote:
> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> > at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> > controller device.
>
On Tue, Jul 8, 2014 at 3:23 AM, Boris BREZILLON
wrote:
> Hello Rob,
>
> On Mon, 7 Jul 2014 23:45:54 -0400
> Rob Clark wrote:
>
>> On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
>> wrote:
>> > The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
>> > at91sam9n12, at91sam9x5 f
On Mon, Jul 7, 2014 at 12:42 PM, Boris BREZILLON
wrote:
> The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller supports at least one primary plane and might
>
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller supports at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller supports at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
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