在 2018-07-18三的 18:26 +0530，Jagan Teki写道：
> On Wed, Jul 18, 2018 at 6:14 PM, Maxime Ripard
> wrote:
> > On Wed, Jul 18, 2018 at 04:24:40PM +0530, Jagan Teki wrote:
> > > Allwinner A64 has display engine pipeline like other Allwinner
> > > SOC's A83T/H3/H5.
> > >
> > > A64 behaviour similar to Allw
Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block Diagram from Allwinner_A64_User_Manual_V1.1.pdf
This is third patch-set followed
On Wed, Jul 18, 2018 at 6:14 PM, Maxime Ripard
wrote:
> On Wed, Jul 18, 2018 at 04:24:40PM +0530, Jagan Teki wrote:
>> Allwinner A64 has display engine pipeline like other Allwinner SOC's
>> A83T/H3/H5.
>>
>> A64 behaviour similar to Allwinner A83T where
>> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
>>
On Wed, Jul 18, 2018 at 04:24:40PM +0530, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block Diagram
On Wed, Jul 18, 2018 at 6:54 PM, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block Diagram from All
