On 2/25/2025 12:55 AM, Tomeu Vizoso wrote:
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file
*file)
+{
+ struct drm_rocket_fini_bo *args = data;
+ struct drm_gem_object *gem_obj;
+ struct rocket_gem_object *rkt_obj;
+ struct drm_gem_shmem_objec
The NPU cores have their own access to the memory bus, and this isn't
cache coherent with the CPUs.
Add IOCTLs so userspace can mark when the caches need to be flushed, and
also when a writer job needs to be waited for before the buffer can be
accessed from the CPU.
Initially based on the same IO
