Re: [PATCH v2 6/6] accel/ivpu: Use cached buffers for FW loading

On 9/26/2023 6:09 AM, Stanislaw Gruszka wrote: From: Karol Wachowski Create buffers with cache coherency on the CPU side (write-back) while disabling snooping on the VPU side. These buffers require an explicit cache flush after each CPU-side modification. Configuring pages as write-combined ma

[PATCH v2 6/6] accel/ivpu: Use cached buffers for FW loading

From: Karol Wachowski Create buffers with cache coherency on the CPU side (write-back) while disabling snooping on the VPU side. These buffers require an explicit cache flush after each CPU-side modification. Configuring pages as write-combined may introduce significant delays, potentially takin