On Wed, Mar 01, 2023 at 11:14:35AM -0700, Jeffrey Hugo wrote:
> On 3/1/2023 10:05 AM, Stanislaw Gruszka wrote:
> > On Wed, Mar 01, 2023 at 09:08:03AM -0700, Jeffrey Hugo wrote:
> > > > This looks a bit suspicious. Are you sure you can modify
> > > > sg->dma_address and still use it as valid value ?
On 3/1/2023 10:05 AM, Stanislaw Gruszka wrote:
On Wed, Mar 01, 2023 at 09:08:03AM -0700, Jeffrey Hugo wrote:
This looks a bit suspicious. Are you sure you can modify
sg->dma_address and still use it as valid value ?
A single entry in the sg table is a contiguous mapping of memory. If it
wasn'
On Wed, Mar 01, 2023 at 09:08:03AM -0700, Jeffrey Hugo wrote:
> > This looks a bit suspicious. Are you sure you can modify
> > sg->dma_address and still use it as valid value ?
>
> A single entry in the sg table is a contiguous mapping of memory. If it
> wasn't contiguous, it would have to be bro
On 2/27/2023 10:14 AM, Stanislaw Gruszka wrote:
On Fri, Feb 24, 2023 at 12:36:51PM -0700, Jeffrey Hugo wrote:
+static int reserve_pages(unsigned long start_pfn, unsigned long nr_pages,
+bool reserve)
+{
+ unsigned long pfn;
+ unsigned long end_pfn = start_pfn
On Fri, Feb 24, 2023 at 12:36:51PM -0700, Jeffrey Hugo wrote:
> > > +static int reserve_pages(unsigned long start_pfn, unsigned long nr_pages,
> > > + bool reserve)
> > > +{
> > > + unsigned long pfn;
> > > + unsigned long end_pfn = start_pfn + nr_pages;
> > > + struct page *page;
On 2/24/2023 8:25 AM, Stanislaw Gruszka wrote:
On Mon, Feb 06, 2023 at 08:41:42AM -0700, Jeffrey Hugo wrote:
+#define SEM_VAL_MASK GENMASK_ULL(11, 0)
+#define SEM_INDEX_MASK GENMASK_ULL(4, 0)
+#define BULK_XFER BIT(3)
+#define GEN_COMPLETION BIT(4)
+#define INBOUND_XFER 1
+#define OUTBO
On Mon, Feb 06, 2023 at 08:41:42AM -0700, Jeffrey Hugo wrote:
> +#define SEM_VAL_MASK GENMASK_ULL(11, 0)
> +#define SEM_INDEX_MASK GENMASK_ULL(4, 0)
> +#define BULK_XFERBIT(3)
> +#define GEN_COMPLETION BIT(4)
> +#define INBOUND_XFER 1
> +#define OUTBOUND_XFER2
> +#define REQ
Add the datapath component that manages BOs and submits them to running
workloads on the qaic device via the dma_bridge hardware. This allows
QAIC clients to interact with their workloads (run inferences) via the
following ioctls along with mmap():
DRM_IOCTL_QAIC_CREATE_BO
DRM_IOCTL_QAIC_MMAP_BO
