Le jeu. 11 mars 2021 à 12:30, Christoph Hellwig a
écrit :
On Sun, Mar 07, 2021 at 08:28:35PM +, Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
possible
to specify that we want GEM buffers backed by non-coherent memory.
Shouldn't there be a way
Le jeu. 11 mars 2021 à 10:27, Hillf Danton a écrit
:
On Wed, 10 Mar 2021 19:01:01 + Paul Cercueil wrote:
Le lun. 8 mars 2021 11:47, Hillf Danton a crit :
On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
poss
On Wed, 10 Mar 2021 19:01:01 + Paul Cercueil wrote:
>Le lun. 8 mars 2021 � 11:47, Hillf Danton a �crit :
>> On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
>>> With the module parameter ingenic-drm.cached_gem_buffers, it is
>>> possible
>>> to specify that we want GEM buffers backe
Hi Hillf,
Le lun. 8 mars 2021 à 11:47, Hillf Danton a écrit :
On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
With the module parameter ingenic-drm.cached_gem_buffers, it is
possible
to specify that we want GEM buffers backed by non-coherent memory.
This dramatically speeds up so
On Sun, 7 Mar 2021 20:28:35 + Paul Cercueil wrote:
> With the module parameter ingenic-drm.cached_gem_buffers, it is possible
> to specify that we want GEM buffers backed by non-coherent memory.
>
> This dramatically speeds up software rendering on Ingenic SoCs, even for
> tasks where write-
With the module parameter ingenic-drm.cached_gem_buffers, it is possible
to specify that we want GEM buffers backed by non-coherent memory.
This dramatically speeds up software rendering on Ingenic SoCs, even for
tasks where write-combine memory should in theory be faster (e.g. simple
blits).
Lea
