[PATCH v2 3/5] drm/xe/regs: fix RING_CTL_SIZE(size) calculation

From: Mingcong Bai Similar to the preceding patch for GuC (and with the same references), Intel GPUs expects command buffers to align to 4KiB boundaries. Current code uses `PAGE_SIZE' as an assumed alignment reference but 4KiB kernel page sizes is by no means a guarantee. On 16KiB-paged kernels,

[PATCH v2 3/5] drm/xe/regs: fix RING_CTL_SIZE(size) calculation

From: Mingcong Bai Similar to the preceding patch for GuC (and with the same references), Intel GPUs expects command buffers to align to 4KiB boundaries. Current code uses `PAGE_SIZE' as an assumed alignment reference but 4KiB kernel page sizes is by no means a guarantee. On 16KiB-paged kernels,