On 2023-04-20 04:11:29, Dmitry Baryshkov wrote:
> On 17/04/2023 23:21, Marijn Suijten wrote:
> > All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
> > the PINGPONG block and into the INTF block. Wire up these interrupts
> > and IRQ masks on all supported hardware.
> >
> > Si
On 17/04/2023 23:21, Marijn Suijten wrote:
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block. Wire up these interrupts
and IRQ masks on all supported hardware.
Signed-off-by: Marijn Suijten
---
.../gpu/drm/msm/disp/dpu1/catalog
On 17.04.2023 22:21, Marijn Suijten wrote:
> All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
> the PINGPONG block and into the INTF block. Wire up these interrupts
> and IRQ masks on all supported hardware.
>
> Signed-off-by: Marijn Suijten
> ---
Acked-by: Konrad Dybci
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block. Wire up these interrupts
and IRQ masks on all supported hardware.
Signed-off-by: Marijn Suijten
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++
.../drm/msm
