Reviewed-by: Lyude Paul
On Mon, 2025-09-22 at 21:30 +1000, Alistair Popple wrote:
> From: Joel Fernandes
>
> Add definition for RISCV_CPUCTL register and use it in a new falcon API
> to check if the RISC-V core of a Falcon is active. It is required by
> the sequencer to know if the GSP's RISCV
On 2025-09-23 at 11:07 +1000, John Hubbard wrote...
> On 9/22/25 12:12 PM, Timur Tabi wrote:
> > On Mon, 2025-09-22 at 21:30 +1000, Alistair Popple wrote:
> >> +
> >> + /// Check if the RISC-V core is active.
> >> + ///
> >> + /// Returns `true` if the RISC-V core is active, `false` other
On Mon, 2025-09-22 at 18:07 -0700, John Hubbard wrote:
> In the spirit of the current "soul" of patchsets, which is "get
> GPU firmware running on Ampere/Ada"), I think let's defer the HALs
> until the first patchset that needs them.
Fair enough, but maybe this patchset should make it clear that i
On 9/22/25 12:12 PM, Timur Tabi wrote:
> On Mon, 2025-09-22 at 21:30 +1000, Alistair Popple wrote:
>> +
>> + /// Check if the RISC-V core is active.
>> + ///
>> + /// Returns `true` if the RISC-V core is active, `false` otherwise.
>> + #[expect(unused)]
>> + pub(crate) fn is_riscv_ac
On Mon, 2025-09-22 at 21:30 +1000, Alistair Popple wrote:
> +
> + /// Check if the RISC-V core is active.
> + ///
> + /// Returns `true` if the RISC-V core is active, `false` otherwise.
> + #[expect(unused)]
> + pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result {
> +
