Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> mutex0 SOF register offset not always 0x30.
> for mt8183, that offset will be 0x2C,
> add this regsiter offset into private data
I think you do two things in this patch. One is mutex0 S
From: Yongqiang Niu
mutex0 SOF register offset not always 0x30.
for mt8183, that offset will be 0x2C,
add this regsiter offset into private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 51 --
1 file changed, 42 insertions(+), 9