Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-19 Thread Eric Anholt
Stephen Boyd writes: > On 05/08, Eric Anholt wrote: >> This is required for the panel to work on bcm911360, where CLCDCLK is >> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the >> CLCDCLK, for platforms that have a settable rate on that one. >> >> v2: Set SET_RATE_PARENT (ca

Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-18 Thread Stephen Boyd
On 05/08, Eric Anholt wrote: > This is required for the panel to work on bcm911360, where CLCDCLK is > the fixed 200Mhz AXI41 clock. The rate set is still passed up to the > CLCDCLK, for platforms that have a settable rate on that one. > > v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend

Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-10 Thread Linus Walleij
On Tue, May 9, 2017 at 8:18 PM, Eric Anholt wrote: > Linus Walleij writes: > >> On Mon, May 8, 2017 at 9:33 PM, Eric Anholt wrote: >> >>> This is required for the panel to work on bcm911360, where CLCDCLK is >>> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the >>> CLCDCLK, f

Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-09 Thread Eric Anholt
Linus Walleij writes: > On Mon, May 8, 2017 at 9:33 PM, Eric Anholt wrote: > >> This is required for the panel to work on bcm911360, where CLCDCLK is >> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the >> CLCDCLK, for platforms that have a settable rate on that one. >> >> v2

Re: [PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-08 Thread Linus Walleij
On Mon, May 8, 2017 at 9:33 PM, Eric Anholt wrote: > This is required for the panel to work on bcm911360, where CLCDCLK is > the fixed 200Mhz AXI41 clock. The rate set is still passed up to the > CLCDCLK, for platforms that have a settable rate on that one. > > v2: Set SET_RATE_PARENT (caught by

[PATCH v2] drm/pl111: Register the clock divider and use it.

2017-05-08 Thread Eric Anholt
This is required for the panel to work on bcm911360, where CLCDCLK is the fixed 200Mhz AXI41 clock. The rate set is still passed up to the CLCDCLK, for platforms that have a settable rate on that one. v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on COMMON_CLK. Signed-off-by: Eri